mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
6eedacd2f7
- Updated test files to change instances of ribp_if to apb4_if in various test cases, ensuring consistency with the new APB4 interface. - Modified assertions and checks in tests to reflect the new APB4 naming conventions, including changes in expected output and input files. - Adjusted the test descriptions to accurately represent the APB4 functionality being tested, particularly in timer, UART, and GPIO tests. - Ensured that all relevant paths and file names in the tests are updated to point to the new APB4 implementations, maintaining the integrity of the test suite.
210 lines
7.3 KiB
Systemverilog
210 lines
7.3 KiB
Systemverilog
`timescale 1ns / 1ps
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module sysctrl_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic fault_valid_i = 1'b0;
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logic [31:0] fault_addr_i = '0;
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logic [ 3:0] fault_wstrb_i = '0;
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logic fault_reserved_i = 1'b0;
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apb4_if apb4 (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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sysctrl_if sysctrl ();
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pll_ctrl_if pll_ctrl ();
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always #5 clk_i = ~clk_i;
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apb4_sysctrl u_sysctrl (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.fault_valid_i (fault_valid_i),
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.fault_addr_i (fault_addr_i),
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.fault_wstrb_i (fault_wstrb_i),
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.fault_reserved_i(fault_reserved_i),
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.apb4 (apb4),
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.sysctrl (sysctrl),
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.pll_ctrl (pll_ctrl)
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);
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task automatic read_register(input logic [31:0] address, output logic [31:0] data);
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begin
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@(negedge clk_i);
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apb4.paddr = address;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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apb4.pwrite = 1'b0;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge clk_i);
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apb4.penable = 1'b1;
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while (!apb4.pready) @(negedge clk_i);
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if (apb4.pslverr !== 1'b0) begin
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$fatal(1, "read %h error=%b expected=%b", address, apb4.pslverr, 1'b0);
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end
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data = apb4.prdata;
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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end
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endtask
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task automatic write_register(input logic [31:0] address, input logic [31:0] data);
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begin
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@(negedge clk_i);
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apb4.paddr = address;
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apb4.pwdata = data;
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apb4.pstrb = 4'hF;
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apb4.pwrite = 1'b1;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge clk_i);
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apb4.penable = 1'b1;
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while (!apb4.pready) @(negedge clk_i);
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if (apb4.pslverr !== 1'b0) begin
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$fatal(1, "write %h error=%b expected=%b", address, apb4.pslverr, 1'b0);
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end
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.pstrb = '0;
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end
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endtask
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logic [31:0] read_data;
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initial begin
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apb4.psel = 1'b0;
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apb4.paddr = '0;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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sysctrl.user_bus_idle_i = 1'b1;
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sysctrl.fault_access_i = 1'b0;
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sysctrl.fault_master_i = '0;
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sysctrl.fault_code_i = `RIB_RESP_RESERVED;
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sysctrl.perf_mgmt_wait_i = 64'd11;
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sysctrl.perf_user_wait_i = 64'd12;
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sysctrl.perf_dma_wait_i = 64'd13;
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sysctrl.perf_apb4_wait_i = 64'd14;
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sysctrl.perf_apb_wait_i = 64'd15;
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sysctrl.perf_sdram_wait_i = 64'd16;
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sysctrl.perf_psram_wait_i = 64'd17;
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sysctrl.perf_flash_wait_i = 64'd18;
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sysctrl.rtc_wake_i = 1'b0;
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pll_ctrl.req_ready_i = 1'b1;
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pll_ctrl.rsp_active_sel_i = '0;
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pll_ctrl.rsp_active_valid_i = 1'b0;
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pll_ctrl.rsp_safe_clk_i = 1'b1;
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pll_ctrl.rsp_pll_lock_i = 1'b0;
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pll_ctrl.rsp_error_i = '0;
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pll_ctrl.rsp_valid_i = 1'b0;
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pll_ctrl.capable_i = 1'b0;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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@(negedge clk_i);
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fault_valid_i = 1'b1;
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fault_addr_i = 32'h1000_F000;
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fault_wstrb_i = 4'hF;
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fault_reserved_i = 1'b1;
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@(negedge clk_i);
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fault_valid_i = 1'b0;
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read_register(32'h1000_B010, read_data);
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if (read_data !== 32'h0000_000B) $fatal(1, "fault status was not recorded");
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read_register(32'h1000_B014, read_data);
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if (read_data !== 32'h1000_F000) $fatal(1, "fault address was not recorded");
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read_register(32'h1000_B018, read_data);
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if (read_data !== 32'h0000_0001) $fatal(1, "fault count was not incremented");
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read_register(32'h1000_B02C, read_data);
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if (read_data !== `RIB_RESP_RESERVED) $fatal(1, "fault detail was not recorded");
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@(negedge clk_i);
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sysctrl.fault_code_i = `RIB_RESP_DECERR;
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fault_valid_i = 1'b1;
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fault_addr_i = 32'hA000_0000;
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fault_wstrb_i = 4'h0;
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fault_reserved_i = 1'b0;
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@(negedge clk_i);
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fault_valid_i = 1'b0;
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read_register(32'h1000_B014, read_data);
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if (read_data !== 32'h1000_F000) $fatal(1, "later fault overwrote first fault address");
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read_register(32'h1000_B018, read_data);
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if (read_data !== 32'h0000_0002) $fatal(1, "later fault did not increment count");
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read_register(32'h1000_B02C, read_data);
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if (read_data !== `RIB_RESP_RESERVED) $fatal(1, "later fault overwrote first fault detail");
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write_register(32'h1000_B010, 32'h0000_0001);
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read_register(32'h1000_B010, read_data);
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if (read_data !== 32'h0000_000A) $fatal(1, "fault W1C did not clear pending");
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write_register(32'h1000_B040, 32'h0000_0005);
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read_register(32'h1000_B044, read_data);
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if (read_data !== 32'd11) $fatal(1, "performance snapshot was not recorded");
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read_register(32'h1000_B020, read_data);
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if (read_data !== 32'h0000_003F) $fatal(1, "user cores were not held in reset");
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write_register(32'h1000_B000, 32'h0000_0006);
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read_register(32'h1000_B024, read_data);
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if ((read_data & 32'h0000_083F) !== 32'h0000_0800) begin
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$fatal(1, "out-of-range user core selection was accepted");
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end
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write_register(32'h1000_B024, 32'h0000_0800);
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write_register(32'h1000_B000, 32'h0000_0001);
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write_register(32'h1000_B020, 32'h0000_003D);
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read_register(32'h1000_B024, read_data);
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if ((read_data & 32'h0000_0300) !== 32'h0000_0300 || (read_data & 32'h1F) != 1) begin
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$fatal(1, "user core start state was not recorded");
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end
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write_register(32'h1000_B020, 32'h0000_003F);
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read_register(32'h1000_B024, read_data);
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if ((read_data & 32'h0000_0300) !== 32'h0000_0200) begin
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$fatal(1, "user core stop state was not recorded");
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end
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read_register(32'h1000_B084, read_data);
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if (read_data !== 32'h0000_0000) begin
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$fatal(1, "test status did not reset");
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end
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write_register(32'h1000_B084, 32'h0000_5A01);
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read_register(32'h1000_B084, read_data);
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if (read_data !== 32'h0000_0000) begin
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$fatal(1, "invalid test status write was accepted");
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end
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write_register(32'h1000_B084, 32'h8000_5A01);
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read_register(32'h1000_B084, read_data);
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if (read_data !== 32'h8000_5A01) begin
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$fatal(1, "test pass status was not recorded");
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end
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write_register(32'h1000_B084, 32'h8000_0B00);
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read_register(32'h1000_B084, read_data);
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if (read_data !== 32'h8000_5A01) begin
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$fatal(1, "terminal test status was overwritten");
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end
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read_register(32'h1000_B088, read_data);
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if (read_data !== 32'h0000_0000) begin
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$fatal(1, "RTC wake status did not reset");
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end
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sysctrl.rtc_wake_i = 1'b1;
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repeat (4) @(posedge clk_i);
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read_register(32'h1000_B088, read_data);
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if (read_data !== 32'h0000_0003) begin
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$fatal(1, "RTC wake live and sticky status was not recorded");
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end
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sysctrl.rtc_wake_i = 1'b0;
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repeat (4) @(posedge clk_i);
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read_register(32'h1000_B088, read_data);
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if (read_data !== 32'h0000_0002) begin
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$fatal(1, "RTC wake sticky status was not retained");
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end
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write_register(32'h1000_B088, 32'h0000_0002);
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read_register(32'h1000_B088, read_data);
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if (read_data !== 32'h0000_0000) begin
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$fatal(1, "RTC wake sticky status W1C failed");
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end
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$display("SystemCtrl register, lifecycle, fault, performance, and RTC wake test passed");
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$finish;
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end
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endmodule
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