mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
db9282aaf6
- Modified DMA error testbench to include crypto input and output AXI4 stream interfaces. - Updated DMA register testbench to integrate crypto AXI4 stream interfaces. - Enhanced SOC IRQ topology test to account for new crypto IRQs. - Added WS2812 DMA testbench modifications for crypto interfaces. - Introduced new Python tests for crypto primitives (AES, SHA, RSA) and APB register paths. - Implemented register parity tests to ensure synchronization between RTL and SDK constants. - Expanded DMA tests to validate crypto streaming endpoints. - Updated memory map tests to include crypto address definitions. - Adjusted SOC topology tests to reflect changes in IRQ mappings and peripheral counts.
213 lines
7.4 KiB
Python
213 lines
7.4 KiB
Python
"""DMA protocol regression tests."""
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from __future__ import annotations
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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def test_dma_reports_native_axi4_errors_bursts_and_streams(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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memory_map = tmp_path / "memory_map"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(memory_map),
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"--have-sram-if",
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"NO",
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],
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check=True,
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)
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source_list = tmp_path / "dma_error.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{memory_map / 'rtl'}",
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f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
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f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl/interface'}",
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f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl/stream'}",
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f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl/utils'}",
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f"+incdir+{ROOT / 'rtl/mini/top'}",
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f"+incdir+{ROOT / 'rtl/ip/peripheral'}",
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_stream_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/fifo.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/stream/round_robin_arbiter.sv"),
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str(ROOT / "rtl/ip/peripheral/dma_pkg.sv"),
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str(ROOT / "rtl/ip/peripheral/dma_req_if.sv"),
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str(ROOT / "rtl/ip/peripheral/dma_axi4_master.sv"),
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str(ROOT / "rtl/ip/peripheral/dma_core.sv"),
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str(ROOT / "tests/rtl/dma_error_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "dma_error_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "dma_error_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "dma_error_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "DMA native AXI4 burst, backpressure, stream, and error test passed" in result.stdout
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def test_dma_apb_registers_and_irq(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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memory_map = tmp_path / "memory_map"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(memory_map),
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"--have-sram-if",
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"NO",
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],
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check=True,
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)
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common = ROOT / "rtl/managed/clusterip/common/rtl"
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source_list = tmp_path / "dma_reg.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{memory_map / 'rtl'}",
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f"+incdir+{common / 'interface'}",
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f"+incdir+{common / 'stream'}",
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f"+incdir+{common / 'utils'}",
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f"+incdir+{ROOT / 'rtl/ip/peripheral'}",
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str(common / "interface/apb4_if.sv"),
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str(common / "interface/axi4_if.sv"),
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str(common / "interface/axi4_stream_if.sv"),
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str(common / "utils/fifo.sv"),
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str(common / "stream/round_robin_arbiter.sv"),
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str(ROOT / "rtl/ip/peripheral/dma_pkg.sv"),
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str(ROOT / "rtl/ip/peripheral/dma_req_if.sv"),
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str(ROOT / "rtl/ip/peripheral/dma_axi4_master.sv"),
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str(ROOT / "rtl/ip/peripheral/dma_reg.sv"),
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str(ROOT / "rtl/ip/peripheral/dma_core.sv"),
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str(ROOT / "rtl/ip/peripheral/apb4_dma.sv"),
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str(ROOT / "tests/rtl/dma_reg_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "dma_reg_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "dma_reg_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "dma_reg_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "DMA APB register and aggregate IRQ test passed" in result.stdout
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def test_dma_crypto_stream_endpoints(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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memory_map = tmp_path / "memory_map"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(memory_map),
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"--have-sram-if",
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"NO",
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],
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check=True,
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)
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common = ROOT / "rtl/managed/clusterip/common/rtl"
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source_list = tmp_path / "dma_crypto.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{memory_map / 'rtl'}",
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f"+incdir+{common / 'interface'}",
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f"+incdir+{common / 'stream'}",
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f"+incdir+{common / 'utils'}",
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str(common / "interface/axi4_if.sv"),
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str(common / "interface/axi4_stream_if.sv"),
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str(common / "utils/fifo.sv"),
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str(common / "stream/round_robin_arbiter.sv"),
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str(ROOT / "rtl/ip/peripheral/dma_pkg.sv"),
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str(ROOT / "rtl/ip/peripheral/dma_req_if.sv"),
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str(ROOT / "rtl/ip/peripheral/dma_axi4_master.sv"),
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str(ROOT / "rtl/ip/peripheral/dma_core.sv"),
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str(ROOT / "tests/rtl/dma_crypto_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "dma_crypto_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "dma_crypto_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "dma_crypto_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "DMA crypto channel 4/5 streaming test passed" in result.stdout
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