- Introduced a new SOC functional architecture diagram in .
- Updated to include instructions for the new SOC diagram, including layout and design specifications.
- Modified to activate changes related to the SOC functional overview.
- Enhanced to include new SOC architecture catalog references.
- Updated to account for the new SOC architecture diagrams in coverage checks.
- Created for validating SOC diagram specifications and ensuring compliance with design rules.
- Added tests in to validate SOC diagram structure and integrity.
- Adjusted existing tests to reflect the addition of SOC architecture coverage.
- Introduced waveform definitions for GA2D operations and exceptions in waveforms.json.
- Added a new Python module for validating CI snapshots and APU implementation details.
- Enhanced diagram coverage validation to ensure accurate reporting of circuit and layout counts.
- Updated programming reference to dynamically calculate read/write credits based on master policies.
- Implemented tests for validating CI snapshot integrity and diagram coverage consistency.
- Added example usage of GA2D fill operation in a new C source file.
- Improved error handling in software reference for IRQ count validation.
- Adjusted diagram reference to check for legacy and version-specific instruction limits.
feat/apu splits the instruction limit into APUMC_MAX_INSTRUCTIONS_V1/V2
with APUMC_MAX_INSTRUCTIONS aliasing the V1 value, so the committed
plain '2048' assignment the drift test mutated no longer exists. Mutate
the alias assignment instead; the drift still disagrees with the RTL
define and must be rejected.
- system-reference.json: APU RX stream tready now feeds the KWS engine
(s_kws_rx_ready) instead of a constant 0
- diagram-layouts.json: APUMC header packs the requested abi word and
entry words mask entry_pc/first_pc/last_pc for APUMC V2
- diagram-storage.json: APU control store implements the 4096-word
(32 KiB) V1.1 refreeze
- diagram-circuits.json: pre-existing GA2D master 6 missing from the two
axi4_data_crossbar master_read_limit bindings (broken on dev before
the merge)
- test_script_tools.py: pre-existing whitespace-strict SOC_SIM_TIME
assertion broken by dev's app.mk alignment change (failed on dev
before the merge); use the test's regex idiom
- Adjusted the native JPEG path to reflect one normal read and one normal write credit for master slot 6 in various documentation files, including README.md, datasheets, and programming references.
- Updated the bus programming section to clarify the admission policy and error handling for the JPEG private path.
- Enhanced the media formats and product use sections to specify the implications of the new credit structure on system integration and performance.
- Modified the RTL implementation to ensure proper credit allocation for the JPEG master in the AXI4 data crossbar.
- Updated regression tests to validate the new credit handling and ensure compliance with the updated specifications.
- Increased simulation timeout for Verilator to accommodate new testing requirements.
- Updated testbench and wrapper test cases to reflect GA2D Phase 5 changes.
- Modified Python test scripts to validate Phase 5 functionality and requirements.
- Enhanced DMA tests for byte-accurate coverage in Phase 5.
- Adjusted register parity tests to include Phase 5 capability and limits.
- Updated publication software tests to reference GA2D Phase 5.
- Changed formal target tests to utilize Phase 5 production hierarchy.
- Updated resource_controller_tb.sv to verify resource STATUS bit layout after HP handoff.
- Modified test_ga2d.py to reflect changes for GA2D Phase 4, including memory map generation and source file handling.
- Introduced new test_ga2d_dma.py for independent FILL/COPY reference-model coverage.
- Updated test_ga2d_platform.py to check for the activation of the private AXI64 master and IRQ routing.
- Adjusted test_ga2d_register_parity.py to validate new scalar encodings for Phase 4.
- Enhanced test_hp_boot_bundle.py to ensure HP boot uses the private GA2D mailbox and resource lifecycle.
- Updated test_hp_platform.py to verify GA2D lifecycle markers and cache handshake budget.
- Modified test_performance_log.py to include GA2D workload and configuration facts in performance logs.
- Adjusted test_publication_retrieval.py and test_publication_software.py to reflect changes in GA2D stages.
- Updated test_script_tools.py to ensure GA2D formal filelists are correctly scoped.
- Refactored test_soc_topology.py to validate the private master policy and active shell in GA2D Phase 4.
- Updated resource_controller_tb.sv to include additional checks for IRQ handling and lifecycle states for GA2D resource.
- Modified soc_irq_topology_tb.sv to accommodate 64-bit IRQ vector handling and updated expectations for IRQ routing.
- Introduced test_ga2d.py for directed verification of GA2D Phase 3 APB4 shell functionality.
- Revised test_ga2d_platform.py to reflect changes in GA2D integration and ensure proper IRQ routing.
- Added test_ga2d_register_parity.py to synchronize GA2D RTL and SDK register constants.
- Updated test_lp_irq.py to reflect changes in IRQ allocation and metadata for GA2D.
- Enhanced test_memory_map.py to verify GA2D MMIO region presence in the memory map.
- Adjusted test_publication_software.py to include GA2D in application results.
- Modified test_soc_topology.py to ensure correct topology generation for GA2D, including IRQ and APB bindings.
- Updated onchip_ram64_tb to increase ID_WIDTH from 6 to 7 and adjusted related write/read tasks.
- Modified resource_controller_tb to accommodate an expanded resource count from 8 to 9, updating related logic signals.
- Enhanced sysctrl_tb to introduce new fault handling logic for data plane faults, including additional fault validation and delivery mechanisms.
- Added tests for clock and reset domains to ensure proper handling of data plane faults and their reset contracts.
- Introduced new test_ga2d_platform.py to verify GA2D Phase 2 functionality, including lifecycle and recovery processes.
- Updated test_soc_topology.py to ensure proper data master policies and validate GA2D integration within the system.
- Enhanced sysctrl.py to ensure the fault master retains the high bit for data plane faults.
- Introduced new CSRs for Hazard3 external interrupts in system_csr.h.
- Expanded the IRQ API in irq.h to include external IRQ enable/disable and priority setting functions.
- Implemented external IRQ handling in system_irq_handler.c, including registration, enabling, and dispatching.
- Created a new source file irq_nocsr.c for CSR-disabled firmware, providing stubs for external IRQ functions.
- Updated booter.c to reflect the new external IRQ count in printed specifications.
- Modified the soc_topology generation script to accommodate 64-bit IRQ vectors and external IRQ count.
- Enhanced the integration tests to validate the new IRQ handling and metadata generation.
- Adjusted various files to ensure compatibility with the new external IRQ architecture, including Verilog modules and test cases.
- Added details about the approved GA2D contract and its phased implementation in resource-controller.md.
- Updated lp-hp-architecture.md to reflect the frozen GA2D specification and its implications for product descriptions.
- Enhanced rtl/README.md with information on the Mini GA2D graphics accelerator's architecture and pending implementation.
- Clarified integration requirements in rtl/mini/integration/README.md regarding GA2D's phased changes and their impact on existing allocations.
- Implemented the KWS engine in the RTL and added necessary components including KWS SRAM client and model loader.
- Enhanced the APU ring scheduler testbench to validate KWS descriptors.
- Introduced new Python tests for KWS functionality, including model import validation, inference checks, and error handling for mutated models.
- Updated existing tests to include KWS components and ensure proper integration within the APU architecture.
- Refactored code for clarity and consistency, including adjustments to signal handling and memory management in test cases.
Added a section detailing the export of the PCLK-synchronized RX warm-flush-busy state as
to the APU's . This change addresses the P7
implementation obligation and clarifies the handling of audio resets and KWS mono pairing
in the context of the I2S interface.
- Enhanced to include instruction families and layouts, improving the APU formats and circuit validation.
- Introduced for handling binary layouts derived from C structures.
- Added to manage APU instruction families and ensure opcode integrity.
- Updated to track global presentation changes, specifically repository footer modifications.
- Created to resolve architectural storage geometry and validate storage configurations.
- Implemented comprehensive tests in and to ensure correctness of diagram coverage and storage geometry.
- Introduced for managing diagram dependencies, validating fields, and collecting diagram data.
- Added to handle version-qualified publication packages, including validation of package integrity and runtime imports.
- Updated to integrate diagram dependencies into source path resolution.
- Created to implement comprehensive tests for diagram validation, package integrity, and runtime import checks.
- Removed unnecessary change markers in fault-reference.typ, linux-runtime.typ, performance-reference.typ, release-verification.typ, software-runtime.typ, usage-appendices.typ.
- Added new timeout and completion semantics in style.md, detailing boot-bundle byte format and API behavior.
- Introduced new API semantics in system-reference.json, including detailed descriptions for various functions.
- Updated software_reference.py to integrate API bundle validation and ensure dependencies are correctly managed.
- Created a comprehensive test suite in test_publication_api_bundle.py to validate API behavior and byte-format tables against actual code.
- Enhanced boot bundle structure with detailed header and entry field specifications, ensuring compliance with serialization and alignment rules.
- Implemented to handle software publication data, including function extraction, dependency validation, and runtime profile management.
- Created to manage publication chapter/IP entries, ensuring structural integrity without affecting pagination.
- Enhanced to integrate software dependencies into the system reference collection process.
- Introduced comprehensive tests in to validate software-derived publication claims and ensure structural integrity of publication entries.
- Implemented to bind final content/navigation page ranges to a baseline and the delivered PDF, including validation of change markers and printed page checks.
- Introduced for publication-only register lookup, including functions for dependencies, validation, register indexing, and diagnostic code handling.
- Updated to include dependencies from the new retrieval reference.
- Created comprehensive tests in to ensure the integrity of retrieval references, diagnostic codes, and report validations.
- Updated to include product details collection.
- Added new sections to datasheets:
- for programming and service procedures.
- summarizing interface standards and supported subsets.
- detailing data formats and interoperability.
- outlining processor configuration and capabilities.
- summarizing reset states and initialization dependencies.
- Introduced for tracing CPU configurations and reset observations.
- Created tests in to validate implementation details and programming results.
- Added new tests for FLAC encoding and decoding, including handling of rice parameters and partial LPC tail.
- Introduced WAV PCM encoding tests to ensure correct behavior across various configurations.
- Updated test cases to validate the handling of malformed FLAC files and metadata structures.
- Enhanced the APU register tests to include expanded P5 profile capabilities and ensure accurate register descriptions.
- Improved assertions for manifest checks in the APU release tests to validate ABI and instruction counts.
- Refactored existing tests for clarity and maintainability, ensuring they align with the latest APU specifications.
- Implemented to handle publication data for routed resources and integer timing/buffer examples.
- Introduced functions for UART, I2C, timer, and I2S timing calculations, along with buffer budget calculations.
- Added validation for programming specifications and constants extraction from source files.
- Updated to integrate programming dependencies into the system reference collection.
- Created comprehensive tests in to ensure the correctness of programming specifications and timing calculations.
- Implemented to validate publication-only system guidance and its evidence dependencies.
- Added functions to check source paths, validate references, and collect system reference data.
- Created comprehensive tests in to ensure proper validation of IP coverage, source dependencies, and report requirements.
- Included tests for various edge cases such as missing sources, duplicate identifiers, and report validation.
- Added to validate publication waveform lanes against SystemVerilog declarations.
- Introduced functions for parsing declarations, checking dimensions, and validating signal properties.
- Created to ensure signal labels refer to valid declarations with correct bit selections.
- Updated waveform styling in for improved visual consistency.
- Introduced a comprehensive rhythm system for consistent spacing across various elements in datasheets.
- Improved heading layout to accommodate chapter openers and section breaks more effectively.
- Updated table styling to ensure proper stroke and spacing, enhancing readability.
- Refined code block and inline code styling for better visibility and consistency.
- Added new tests to validate the preservation of list structures and typography rules in publications.
- Enhanced waveform rendering with improved color handling and SVG styling.
This commit introduces a new test suite for validating publication register data, ensuring that real ABI values and complete bit layouts are retained. The tests cover various scenarios including register interface checks, field overlap validation, duplicate offsets, reset value checks, and more. Additionally, it verifies that API listings contain only declarations and that page validation rejects shared start pages.
- Introduced a new overview section detailing the product features and specifications for the retroSoC Mini.
- Created a comprehensive peripherals section outlining memory interfaces, GPIO, DMA, timers, multimedia, and encryption components.
- Added a pins section that includes pin mapping, GPIO alternate-function matrix, and electrical specifications.
- Developed a software section covering boot sequence, runtime environment, applications, and Linux driver status.
- Established a style file to define the visual presentation of the datasheet.
- Implemented tests for validating datasheet generation and ensuring integrity of engineering inputs.
- Modified the capability register value in apu_reg_tb.sv to 0x01bd.
- Simplified rejected write checks for the COMMAND register in apu_reg_tb.sv.
- Added backend build ID input to the ring scheduler testbench.
- Updated test cases in test_apu.py to include new codec transport and controller files.
- Created new test file test_apu_codec_transport.py for APU-P5 transport assembler and parser tests.
- Added codec profile and dependency tests in test_apu_codecs.py.
- Enhanced register parity tests to include P5 primitive mask.
- Improved script tools tests for file download functionality and dependency helpers.
- Modified test_apu_register_parity.py to reflect changes in P4 ISA definitions.
- Updated test_apu_register_parity.py to include new manifest entries for P4.
- Enhanced test_script_tools.py to include checks for APU primitives filelists.
- Added assertions for APU primitives in the formal filelists test to ensure proper scoping and inclusion.
- Introduced new test cases for APU-P3 loader, control store, and sequencer functionality in .
- Enhanced the APU ring scheduler and stream router testbenches to validate reset timing and state transitions.
- Added comprehensive tests for APU microcode tools, ensuring assembler and interpreter consistency.
- Updated register parity tests to synchronize APU RTL and SDK ABI across P3.
- Expanded formal filelist generation to include APU loader and sequencer.
- Improved SBY configuration for formal verification with Bitwuzla.
- Updated axi4_async_bridge_tb.sv to include unilateral reset handling in the test.
- Enhanced axi4_target_guard_tb.sv with a new task for read beat normalization and additional read tests.
- Introduced hp_axi4_mux3_rr_tb.sv to test round-robin arbitration for multiple AXI4 interfaces.
- Expanded test_apu.py to include tests for APU stream router, DMA, ring scheduler, and integrated DMA/ring/backend functionality.
- Added new test cases for APU-P2 Gateway A round-robin fairness.
- Updated test_clock_reset_domains.py to include APU data crossing.
- Enhanced test_script_tools.py to scope formal filelists for APU and Gateway A.
- Introduced new task in for handling high-performance APU writes with access fault checks.
- Updated to support an expanded resource count, including ownership and IRQ routing for the new APU resource.
- Enhanced to validate IRQ expectations for the newly added APU resource.
- Created for directed verification of APU-P1 APB4 register shell and integrated IRQ ownership topology.
- Added to ensure synchronization between RTL and SDK register ABI.
- Modified to parameterize tests for product modes, improving flexibility in testing.
- Updated to reflect changes in APU memory mapping and ensure correct assertions.
- Enhanced to validate the complete IRQ and resource allocations for the APU.
- Introduced a description of the planned Mini Audio Processing Unit (APU) architecture.
- Included information about the coreless architecture, microcode bundle, and hardware sequencer functionalities.
- Mentioned the continuous KWS feature and its current implementation status.
- Linked to the relevant documentation for further details on the APU.
- Introduced
etrosoc-mini-feature-design skill for researching and freezing new SoC/IP features.
- Added
etrosoc-mini-feature-implementation skill for preflight and implementation of approved phases.
- Created
etrosoc-mini-feature-review skill for diagnosing failures and reviewing feature compliance.
- Developed corresponding YAML configurations and evaluation tests for each skill.
- Included a specification template for IP documentation and updated CODEOWNERS for agent directory.
- Enhanced tests to validate skill metadata, evaluation completeness, and manual input contracts.
- Updated to integrate a coefficient engine and additional signals for coefficient handling.
- Modified to include a coefficient engine, enhancing the encoding process with new signals.
- Improved to validate generated blocks against expected values and added timeout handling.
- Introduced for testing SRAM wrappers in JPEG workspace.
- Enhanced test coverage in to reject invalid STA net drivers.
- Updated to ensure proper coverage of canonical domains in timing contracts.
- Added a new test for JPEG coefficient engine in .
- Improved memory map tests in to validate public active MMIO regions.
- Enhanced management core specification tests in to verify high-performance core specifications.
- Added behavioral-only checks in to exclude synthesis and netlist consumers.
- Updated SDRAM tests in to track active firmware memory.
- Enhanced STA constraints tests in to cover current clock domains and net drivers.
- Implemented tests for the deterministic baseline JPEG reference model in , covering encoding, decoding, quality scaling, and error handling.
- Created to ensure synchronization between RTL and C register constants for JPEG.
- Updated to reflect changes in the number of APB interfaces and IRQ mappings, ensuring the topology generates correct bindings.
- Introduced and its corresponding testbench to monitor fabric interactions.
- Updated to include additional checks for ACL and QoS, enhancing the test coverage.
- Modified to include the new fabric monitor file.
- Created a new test file to validate the functionality of the fabric monitor.
- Updated to integrate the fabric monitor interface.
- Adjusted to reflect changes in the AXI4 data crossbar test output.
- Enhanced to ensure proper generation of connections for the fabric monitor.
- Updated user extension tests to account for new local SRAM and stream definitions.
- Introduced to validate AXI4 interface for 64-bit on-chip SRAM.
- Added to test resource controller functionality including ownership, IRQ handling, and cache handshake.
- Updated to include resource controller interface.
- Enhanced to cover additional IRQ scenarios.
- Added new tests in for AXI4 target guard timeout and isolation.
- Updated to reflect changes in the high-performance profile.
- Modified to verify on-chip SRAM bank configurations.
- Added for directed verification of resource controller.
- Updated to check SDRAM mapped window coverage.
- Enhanced to ensure correct IRQ mappings and APB target generation.
- Implemented tests for AXI4 async bridge functionality, including transfer and warm flush scenarios.
- Added tests for AXI4 data crossbar to validate concurrent outstanding requests and ACL handling.
- Introduced clock frequency monitor tests to ensure detection of clock stop and restart events.
- Developed tests for extension DMA master to verify copy operations, tail strobe behavior, and timeout handling.
- Created tests for HP lifecycle controller to validate drain, flush, and forced reset functionalities.
- Updated existing test scripts to include new RTL components and ensure proper simulation configurations.
- Added interface to and implemented error handling for register writes.
- Introduced a new test for AXI4 address gate functionality in .
- Updated clock and reset domain assertions in to reflect new domain names.
- Modified expected outputs in to include new clock domains.
- Adjusted chip configuration assertions in to account for additional power pads.
- Enhanced memory map tests in with new definitions and includes.
- Updated pin mapping tests in to include new reference clock pads.
- Improved script tools tests in to ensure correct validation of extension bindings.
- Refined system control tests in to include new clock control interface.
- Updated USB2 packet RAM tests in to include new SRAM definitions.
- Enhanced user extensions tests in to validate new product extension configurations.
- Adjusted user IP register parity tests to use legacy extensions.
- Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
- Introduced target in Makefile to run fast-flash HP Linux userspace acceptance tests with a 7200-second simulation time limit.
- Updated documentation to describe the new fast-flash model and its usage in simulations.
- Implemented Verilator-specific XPI core and fast flash model to handle slot-0 read operations with improved performance.
- Added new tests for the XPI fast flash model to verify protocol compliance and error handling.
- Enhanced existing tests to ensure proper integration of fast-flash features in the HP Linux simulation flow.
- Added TCD head and count registers to DMA definition and register files.
- Introduced CRC expected and result registers for enhanced error checking.
- Updated DMA version to 2.0 to reflect new features.
- Modified DMA testbench to validate new TCD and CRC functionalities.
- Enhanced README and filelists to include new dependencies and configurations.
- Updated formal verification and runtime tests to accommodate new DMA features.
- Updated axi4_interconnect_tb to include an additional master and issue high-priority access tests.
- Introduced hp_mailbox_tb for testing the HP mailbox functionality, including register and doorbell operations.
- Added plic_tb to validate PLIC priority, claim, and completion mechanisms.
- Enhanced pll_ctrl_tb to initialize additional system control signals.
- Updated soc_irq_topology_tb to account for new IRQ sources and validate IRQ signal behavior.
- Improved sysctrl_tb to include tests for HP lifecycle control and status registers.
- Added tests for HP boot bundle layout, CRC, and payload validation.
- Introduced test_hp_mailbox.py for RTL regression testing of the HP mailbox.
- Added test_hp_platform.py to validate HP platform configuration and generated-source boundaries.
- Enhanced test_librelane_flow.py to ensure correct signal placement in chip configuration.
- Added performance log tests to validate LP and HP coremark ratios.
- Updated test_soc_topology.py to reflect changes in IRQ and peripheral mappings.
- Introduced a new ECC directory containing scripts and Makefile for the padless ICS55 core hardening flow.
- Updated the main Makefile to include the new ECC Makefile and added relevant help commands.
- Added dependencies for the ECC CLI in the dependencies.lock.json file.
- Created README documentation for the ECC flow detailing usage and requirements.
- Implemented various scripts for configuration generation, validation, output checking, and packaging of ECC results.
- Added unit tests to validate the ECC configuration and flow behavior.
- Introduced to handle the preparation of the SKY130 OpenRAM SRAM views.
- Updated to download and prepare the SRAM archive during PDK setup.
- Enhanced OpenSTA and Yosys configurations to accommodate SRAM macro integration.
- Added Verilog simulation models for GF180 and SKY130 SRAM macros.
- Implemented tests for SRAM setup and validation, ensuring correct integration and functionality.
- Updated various Makefiles and scripts to support SRAM size and macro configurations.
- Updated multiple RTL files in the and directories to include licensing information under the Mulan PSL v2.
- Added attribution comments for contributions from ETH Zurich and University of Bologna in .
- Enhanced test files in the directory with licensing details and ensured compliance with the Solderpad Hardware License, Version 0.51.
- Introduced a new test in to verify the preservation of attribution for PULP HyperBus sources.
- Updated filelist to include sg13g2_udp.v for IHP130.
- Modified sdram_axi4.sv to initialize read and write control signals.
- Enhanced clock and reset domain configuration to include jtag_trst_n_i_pad.
- Updated iverilog.mk to support IHP130 in tech-cell-test.
- Enhanced pin_map generation to include power pads for IHP130.
- Updated tc_io modules to handle power pins for IHP130.
- Added timing contract generation in package.py for commercial flow.
- Enhanced test cases to validate new IHP130 features and configurations.
- Added new tests for LibreLane flow specific to IHP130.
- Introduced and for STA flow, enabling scenario loading and timing analysis.
- Added for synthesis flow, defining the synthesis process and generating reports.
- Implemented for synthesis, including library handling and design checks.
- Enhanced to support additional filelists and include directories for SOC export.
- Added ICS55 PLL implementation in with corresponding testbench .
- Created comprehensive tests in for various flow components and scenarios.
- Updated to forward new filelist arguments for SOC generation.
- Improved to validate source export functionality and ensure proper file handling.
- Added i2c_if.sv and spi_if.sv to rtl_style_audit.json for proper inclusion in style checks.
- Updated test_i2c.py to reference i2c_if.sv from the serial directory instead of the cluster IP directory.
- Modified test_spisd.py to point to spi_if.sv in the storage directory instead of the cluster IP directory.
- Deleted references to XEZIM and CVC in the Makefile and related scripts.
- Removed XEZIM-specific and CVC-specific files, including external memory models and SRAM models.
- Updated the test suite to reflect the removal of XEZIM and CVC simulators, ensuring no broken references remain.
- Cleaned up the README and doctor scripts to remove mentions of XEZIM and CVC.
- Updated the testbench to conditionally include pull-up resistors and reset hold time based on the selected simulator.
- Enhanced the filelist generation script to support both XEZIM and CVC formats, allowing for simulator-specific options and exclusions.
- Introduced new makefiles ( and ) to handle compilation and simulation for the respective backends.
- Added external memory models and SRAM models specifically for XEZIM simulations.
- Created a test suite to validate the integration of optional simulator backends and ensure they do not interfere with the default backend.
- Updated README.md to clarify the status of KianV RV32IMA and PicoRV32 in the user-extension map.
- Modified Makefile to include USER_EXTENSIONS_SOURCE in MPW variant stamp dependencies.
- Enhanced integration README.md to better describe the relationship between user_extensions.json and mpw.toml.
- Updated generate_user_extensions.py to include design_id in ExtensionTarget and enforce unique design IDs.
- Changed user_extensions.json schema version to 2 and added design_id fields for core and IP targets.
- Refactored generate_mpw.py to support the new manifest structure and validate design selections.
- Adjusted sysctrl_tb.sv test cases to reflect changes in user core reset states.
- Enhanced test_opipsram.py to utilize ccache for improved compilation performance.
- Updated test_script_tools.py to include new tests for active manifest generation.
- Modified test_user_extensions.py to validate isolated scalar bindings and reject duplicate design selections.
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine.
- Updated clock and reset domain tests to include USB2 ULPI crossings.
- Enhanced memory map tests to verify USB2 base addresses and performance offsets.
- Modified pin map tests to ensure USB2 ULPI pins are correctly generated.
- Updated SOC topology tests to account for USB2 peripherals and IRQ mappings.
- Added static timing analysis constraints for USB2 clock domains.
- Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine.
- Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
- Updated filelist to include new XPI source files.
- Modified IRQ compatibility mapping for XPI in the SOC topology generator.
- Adjusted JSON topology configuration to reflect new IRQ signal naming.
- Changed software.mk to reference the new XPI HAL source file.
- Enhanced APB4 peripheral module to include XPI IRQ signal.
- Updated RTL style audit to include new XPI files.
- Documented new XPI programming script in README.
- Added a new script for programming XPI flash through OpenOCD.
- Enhanced XPI IO testbench to validate new LUT engine and isolation behavior.
- Created unit tests for the new XPI programming tool and its functionalities.
- Increased the number of masters in the AXI4 interconnect testbench from 5 to 6.
- Added new testbench for SPI-SD clock functionality (spisd_clock_tb).
- Introduced testbench for SPI-SD command engine (spisd_command_tb).
- Created testbench for SPI-SD CRC calculation (spisd_crc_tb).
- Implemented testbench for SPI-SD data handling (spisd_data_tb).
- Developed wrapper testbench for SPI-SD with APB and training checks (spisd_wrapper_tb).
- Added Python test suite for SPI-SD RTL regressions (test_spisd.py).
- Created a test for verifying register parity between RTL and C header definitions (test_spisd_register_parity.py).
- Introduced a new testbench for the SDIO wrapper () to validate APB interactions.
- Updated to include IRQ handling for SDIO0 and SDIO1.
- Enhanced to account for performance management of SDIO0 and SDIO1.
- Modified memory map tests to include SDIO base addresses and performance wait offsets.
- Updated pin mapping tests to include SDIO1 signals.
- Created a comprehensive suite of SDIO tests () covering various functionalities including CRC, command engine, DMA, and standalone operations.
- Added a new test for verifying SDIO register parity against the RTL definition.
- Adjusted SOC topology tests to reflect the addition of SDIO in the IRQ and APB fabric.
- Updated memory map tests to include OPI PSRAM address and size definitions.
- Introduced new test suite for OPI PSRAM to ensure RTL and HAL ABI consistency.
- Enhanced script tools tests to validate formal filelists for OPI PSRAM.
- Modified SOC topology tests to incorporate OPI PSRAM bindings and IRQ mappings.
- Introduced to define formal properties for the DMA design, ensuring correct behavior under various conditions.
- Created as a testbench for the DMA register interface, implementing APB and AXI4 protocols to validate register operations.
- Added to verify synchronization between RTL and SDK register constants, ensuring consistency across implementations.
- Introduced burst length handling in the SDRAM Verilator model, allowing for more flexible read/write operations.
- Added new SDRAM-related source files to the project structure, including sdram_pkg.sv and sdram_axi4.sv.
- Updated software makefile to include new SDRAM-related C source files for HAL.
- Enhanced C test suite with new tests for SDRAM timing and functionality, ensuring proper integration with the HAL.
- Improved RTL testbench for SDRAM, adding support for burst writes and reads, and verifying data integrity.
- Updated Python test scripts to reflect changes in SDRAM handling and ensure comprehensive coverage of SDRAM functionality.
- Added checks to ensure register offsets between RTL and HAL definitions match, maintaining consistency across the codebase.
- Updated the PSRAM register module to include additional signals for better control and data management.
- Introduced dedicated signals for each register's data and enable lines, enhancing clarity and maintainability.
- Replaced synchronous assignments with combinational logic for register updates.
- Added new D flip-flops for various control signals to ensure proper synchronization.
- Improved the performance control logic to reset counters based on specific conditions.
- Minor formatting adjustments in the I2S register and APB4 I2S modules for consistency.
- Updated test script to include additional utility files for comprehensive testing.
maksyuki