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maksyuki 795b3a4b1d feat: add fast-flash support for Verilator simulation and XPI model

- Introduced  target in Makefile to run fast-flash HP Linux userspace acceptance tests with a 7200-second simulation time limit.
- Updated documentation to describe the new fast-flash model and its usage in simulations.
- Implemented Verilator-specific XPI core and fast flash model to handle slot-0 read operations with improved performance.
- Added new tests for the XPI fast flash model to verify protocol compliance and error handling.
- Enhanced existing tests to ensure proper integration of fast-flash features in the HP Linux simulation flow.

2026-08-28 11:29:52 +08:00

feat: enhance DMA functionality with TCD and CRC support

2026-08-28 08:42:36 +08:00

rtl

feat: add fast-flash support for Verilator simulation and XPI model

2026-08-28 11:29:52 +08:00

README.md

feat: add fast-flash support for Verilator simulation and XPI model

2026-08-28 11:29:52 +08:00

test_axi4.py

feat: add HP mailbox and PLIC tests; enhance existing test coverage

2026-08-27 19:26:32 +08:00

test_clint.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_clock_reset_domains.py

feat: add USB2 support and related tests

2026-08-22 07:15:41 +08:00

test_commercial_flow.py

fix: fix the wrong timing para for commercial flow

2026-08-24 07:39:09 +08:00

test_crypto_register_parity.py

feat: add crypto accelerator support and related tests

2026-08-21 07:29:00 +08:00

test_crypto.py

feat: add crypto accelerator support and related tests

2026-08-21 07:29:00 +08:00

test_dma_register_parity.py

feat: add formal verification properties for DMA design and corresponding testbench

2026-08-18 16:54:55 +08:00

test_dma.py

feat: add crypto accelerator support and related tests

2026-08-21 07:29:00 +08:00

test_dvp.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_ecc_flow.py

feat: add ECC flow for padless ICS55 core hardening

2026-08-25 20:02:58 +08:00

test_gpio.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_hp_boot_bundle.py

feat: add HP mailbox and PLIC tests; enhance existing test coverage

2026-08-27 19:26:32 +08:00

test_hp_mailbox.py

feat: add HP mailbox and PLIC tests; enhance existing test coverage

2026-08-27 19:26:32 +08:00

test_hp_platform.py

feat: add fast-flash support for Verilator simulation and XPI model

2026-08-28 11:29:52 +08:00

test_i2c.py

refactor: refactor RTL source paths in style audit and test files

2026-08-22 19:47:40 +08:00

test_i2s.py

feat: add I2S support with formal verification and testbench

2026-08-17 15:53:39 +08:00

test_librelane_flow.py

feat: enhance DMA functionality with TCD and CRC support

2026-08-28 08:42:36 +08:00

test_memory_map.py

feat: improve the performance of the onchip sram ctrl

2026-08-24 20:10:22 +08:00

test_mgmt_core_spec.py

feat: improve the performance of the onchip sram ctrl

2026-08-24 20:10:22 +08:00

test_mgmt_debug.py

feat: add management debug reset and JTAG integration for Hazard3

2026-08-05 22:30:11 +08:00

test_onchip_ram.py

feat: Add support for SKY130 OpenRAM SRAM integration

2026-08-25 12:55:47 +08:00

test_onchip_sram_register_parity.py

feat: improve the performance of the onchip sram ctrl

2026-08-24 20:10:22 +08:00

test_opipsram.py

docs: add licensing information and attribution comments to various RTL and test files

2026-08-24 10:02:48 +08:00

test_performance_log.py

feat: add HP mailbox and PLIC tests; enhance existing test coverage

2026-08-27 19:26:32 +08:00

test_pin_map.py

feat: add syn and floorplan design for librelane

2026-08-24 20:11:14 +08:00

test_plic.py

feat: add HP mailbox and PLIC tests; enhance existing test coverage

2026-08-27 19:26:32 +08:00

test_psram.py

refactor: refactor PSRAM register module for improved signal handling and add new signals

2026-08-17 17:17:43 +08:00

test_repository_layout.py

refactor: refactor RTL paths and update test descriptions

2026-08-13 13:41:52 +08:00

test_rib2apb.py

feat: refactor RIB to APB bridge and update related components

2026-08-05 16:03:41 +08:00

test_rib.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_rtl_connection_migration.py

style: refactor error handling in rib modules and improve RTL naming conventions

2026-08-12 22:18:19 +08:00

test_rtl_readiness.py

feat: add RTL readiness checks and validation scripts for synthesis intent

2026-08-13 10:59:33 +08:00

test_rtl_style.py

refactor: refactor RTL style checker and update test cases

2026-08-15 08:33:27 +08:00

test_script_tools.py

feat: enhance DMA functionality with TCD and CRC support

2026-08-28 08:42:36 +08:00

test_sdio_register_parity.py

feat: add SDIO support and related tests

2026-08-20 10:03:51 +08:00

test_sdio.py

feat: add SDIO support and related tests

2026-08-20 10:03:51 +08:00

test_sdram.py

feat: enhance SDRAM Controller and Testbench Functionality

2026-08-18 09:06:19 +08:00

test_sky130_sram_setup.py

feat: Add support for SKY130 OpenRAM SRAM integration

2026-08-25 12:55:47 +08:00

test_soc_topology.py

feat: add HP mailbox and PLIC tests; enhance existing test coverage

2026-08-27 19:26:32 +08:00

test_spisd_register_parity.py

feat: add SPI-SD RTL tests and enhance interconnect testbench

2026-08-20 16:12:15 +08:00

test_spisd.py

refactor: refactor RTL source paths in style audit and test files

2026-08-22 19:47:40 +08:00

test_sta_constraints.py

feat: Add support for SKY130 OpenRAM SRAM integration

2026-08-25 12:55:47 +08:00

test_sysctrl.py

feat: add HP mailbox and PLIC tests; enhance existing test coverage

2026-08-27 19:26:32 +08:00

test_tech_cell_config.py

feat: refactor NMI interface and remove unused variables

2026-07-26 09:03:33 +08:00

test_timer.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_uart.py

refactor: refactor tests to replace RIBP references with APB4 equivalents

2026-08-16 21:19:20 +08:00

test_usb2_register_parity.py

feat: add USB2 support and related tests

2026-08-22 07:15:41 +08:00

test_usb2.py

feat: implement SRAM support for ICS55 in tc_usb2_packet_ram and add corresponding test

2026-08-23 12:04:13 +08:00

test_user_extensions.py

feat: refactor user extension handling and update MPW generation

2026-08-22 10:53:03 +08:00

test_user_ip_register_parity.py

feat: implement user IP integration with demo and validation tests

2026-08-21 09:18:20 +08:00

test_ws2812.py

feat: add formal verification properties for DMA design and corresponding testbench

2026-08-18 16:54:55 +08:00

test_xpi_fast_flash.py

feat: add fast-flash support for Verilator simulation and XPI model

2026-08-28 11:29:52 +08:00

test_xpi_flash_tool.py

feat: refactor XPI integration and add programming tool

2026-08-20 20:48:36 +08:00

test_xpi_io.py

feat: refactor XPI integration and add programming tool

2026-08-20 20:48:36 +08:00

test_yosys_synth_recipes.py

feat: enhance synthesis and metrics handling with recipe-specific outputs and configurations

2026-08-20 12:38:28 +08:00

README.md

Repository Tests

This directory contains tests for deterministic SDK behavior and build/quality tooling.

c/test_runtime.c is the host C test program used by make sw-host-test.
test_script_tools.py covers setup, dependency, filelist, warning, metric, archive, and regression-helper behavior.
test_rtl_readiness.py covers the machine-readable RTL maturity and synthesis-intent checks.
test_rtl_style.py covers ownership, named connections, and staged naming rules for new owned RTL.
test_crypto.py runs directed AES, SHA-2, RSA/Montgomery, streaming, and APB4 simulations; test_crypto_register_parity.py checks the handwritten RTL/C register ABI and test_dma.py covers DMA bursts, TCD fetch, CRC, tail-byte writes, and crypto endpoints.
test_user_ip_register_parity.py keeps the integrated slot 1 timer and slot 2 GPIO register offsets synchronized with their application-owned C definitions and checks their extension-manifest slot assignments.
test_hp_boot_bundle.py checks the HP flash ABI, CRCs, payload placement, and handwritten mailbox RTL/C offset parity. test_hp_platform.py, test_hp_mailbox.py, test_plic.py, and the AXI tests cover the remaining HP integration contracts. test_xpi_fast_flash.py covers the explicitly selected Verilator slot-0 read accelerator, including backpressure and negative completion paths.

Add a host C test when changing deterministic runtime or media logic; add a Python test when changing scripts or build policy. Run:

make sw-host-test
python3 -m pytest -q

These tests complement, but do not replace, firmware builds, RTL simulation, synthesis, timing, or hardware validation.