maksyuki
8ba8a0ad47
- Updated axi4_interconnect_tb to include an additional master and issue high-priority access tests. - Introduced hp_mailbox_tb for testing the HP mailbox functionality, including register and doorbell operations. - Added plic_tb to validate PLIC priority, claim, and completion mechanisms. - Enhanced pll_ctrl_tb to initialize additional system control signals. - Updated soc_irq_topology_tb to account for new IRQ sources and validate IRQ signal behavior. - Improved sysctrl_tb to include tests for HP lifecycle control and status registers. - Added tests for HP boot bundle layout, CRC, and payload validation. - Introduced test_hp_mailbox.py for RTL regression testing of the HP mailbox. - Added test_hp_platform.py to validate HP platform configuration and generated-source boundaries. - Enhanced test_librelane_flow.py to ensure correct signal placement in chip configuration. - Added performance log tests to validate LP and HP coremark ratios. - Updated test_soc_topology.py to reflect changes in IRQ and peripheral mappings.
Build and Quality Scripts
This directory contains the Python implementation of setup, dependency locking, build manifests, flow execution, simulation checks, regression orchestration, quality checks, metrics, packaging, and cleanup.
Scripts are part of the build contract. Prefer existing helpers over ad-hoc
shell behavior, preserve structured JSON results, and keep setup/download
behavior controlled by dependencies/dependencies.lock.json.
development_environment.py is the shared Docker, Nix, and manual bootstrap
entry point. It installs only the checksum-verified open-source tool bundles and
hash-pinned Python dependencies; project-local PDK and source setup remains under
the existing Make targets.
publish_fatfs_artifact.sh is the manual release helper for the lock-pinned
FatFs R0.16 archive. It verifies the archive, GitHub authentication, release
absence, and the published asset checksum before reporting the checksum-pinned
URL.
parse_performance_log.py converts the APP=benchmark UART PERF records
into meta/performance.json. The parser requires the terminal
PERF_BENCHMARK_PASS marker. parse_coremark_log.py converts the fixed
SRAM CoreMark quick report into meta/coremark.json; it requires one valid
COREMARK_RESULT record and COREMARK_PASS. Both reports complement, rather
than replace, the common SIM_TEST_PASS simulation verdict.
generate_vexiiriscv.py verifies the locked VexiiRiscv revision and generates
the fixed HP core below build/; generated RTL is never tracked.
setup_hp_linux.py installs the locked OpenSBI, Linux, and Buildroot revisions
and can resume a checkout left without HEAD by an interrupted fetch.
build_hp_linux.py builds the RV32 ilp32d image set with the repo-owned
external OpenSBI platform. package_hp_boot.py creates the v1 LP/HP flash
bundle and its SHA-256/CRC manifest. check_lp_hp_performance.py applies the
measured 2.5x CoreMark/MHz gate.
run_debug_session.py is the local Hazard3 debug acceptance driver. It starts
the Verilator remote-bitbang endpoint, the lock-pinned OpenOCD binary, and
RISC-V GDB, then records their logs and a structured result. Invoke it through
make CONFIG=configs/ci/ihp130-debug.mk SIMU=VERILATOR debug-sim; see
../docs/hazard3-debug.md for its scope and
limitations.
program_xpi_flash.py drives the SRAM-resident XPI loader through an existing
OpenOCD GDB endpoint. It validates and splits a BIN at 4 KiB sector boundaries,
generates a reviewable GDB script, and performs erase/program only when
--execute is explicit. See ../docs/ip/xpi.md.
check_rtl_style.py applies the ownership-aware RTL style rules from
../rtl/rtl_style_manifest.json. The CI
target checks changed self-owned RTL for positional module connections, legacy
constructs, and the staged naming contract. rtl-style-check-all retains the
historical full-tree structural baseline while naming debt is migrated in
module-sized batches. Existing findings must not be expanded by a new change.
migrate_rtl_connections.py is the conservative migration helper for legacy
positional instances. It discovers ANSI-style module declarations in the
production RTL and locked technology/IP trees, rewrites only exact positional
parameter and port lists to named connections, and reports ambiguous instances
without modifying them. Run make rtl-migrate-connections, then
make rtl-format rtl-style-check; review the generated diff before committing.
migrate_rtl_names.py shortens only local identifiers beginning with s_ or
r_ (plus local automatic variables such as read_request). Public module
ports and interface fields are intentionally unchanged. Run
make rtl-migrate-names, then format and lint the resulting diff.
Update or add tests in ../tests for script behavior. Run
ruff check . and python3 -m pytest -q; build-flow changes also require the
relevant dry-run or regression profile from AGENTS.md.