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- Removed UART files from clusterip and updated file lists accordingly. - Added new UART flow control module and interface to manage RTS/CTS signals. - Updated UART formal verification files to include new flow control signals. - Modified UART testbench to validate flow control behavior and updated test cases. - Adjusted top-level design to integrate new UART interface and signal connections. - Enhanced GPIO pin mapping to accommodate new UART control signals. - Updated linting and formal generation scripts to reflect changes in UART structure.