mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
942ca936bf
- Updated filelist to include sg13g2_udp.v for IHP130. - Modified sdram_axi4.sv to initialize read and write control signals. - Enhanced clock and reset domain configuration to include jtag_trst_n_i_pad. - Updated iverilog.mk to support IHP130 in tech-cell-test. - Enhanced pin_map generation to include power pads for IHP130. - Updated tc_io modules to handle power pins for IHP130. - Added timing contract generation in package.py for commercial flow. - Enhanced test cases to validate new IHP130 features and configurations. - Added new tests for LibreLane flow specific to IHP130.
116 lines
4.6 KiB
Python
116 lines
4.6 KiB
Python
"""Tests for the single-level IHP130 LibreLane pad-ring flow."""
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from __future__ import annotations
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import importlib.util
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import json
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from pathlib import Path
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from types import SimpleNamespace
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ROOT = Path(__file__).resolve().parents[1]
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PIN_MAP = ROOT / "rtl/mini/pin_map/pin_map.json"
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DOMAINS = ROOT / "rtl/mini/integration/clock_reset_domains.json"
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FLOW_ROOT = ROOT / "physical/librelane"
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def load_module(name: str, path: Path):
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spec = importlib.util.spec_from_file_location(name, path)
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assert spec is not None and spec.loader is not None
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module = importlib.util.module_from_spec(spec)
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spec.loader.exec_module(module)
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return module
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def chip_arguments(tmp_path: Path) -> SimpleNamespace:
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return SimpleNamespace(
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pin_map=PIN_MAP,
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rtl=tmp_path / "retrosoc_asic_sources.sv",
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sdc=tmp_path / "retrosoc_asic.sdc",
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pdn=FLOW_ROOT / "pdn_cfg.tcl",
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bondpad_gds=tmp_path / "bondpad_70x70.gds",
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bondpad_lef=FLOW_ROOT / "bondpad/bondpad_70x70.lef",
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sram_vh=FLOW_ROOT / "sram_blackboxes.vh",
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ext_clk_hz=72_000_000,
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aud_clk_hz=18_432_000,
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have_pll=False,
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output=tmp_path / "config.json",
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)
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def test_chip_config_places_every_signal_and_power_pad_once(tmp_path: Path) -> None:
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module = load_module("retrosoc_librelane_config", FLOW_ROOT / "scripts/generate_chip_config.py")
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config = module.build_config(chip_arguments(tmp_path))
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sides = {name: config[f"PAD_{name.upper()}"] for name in module.SIDE_ORDER}
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placed = [instance for side in module.SIDE_ORDER for instance in sides[side]]
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assert len(placed) == 189
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assert len(placed) == len(set(placed))
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assert {side: len(instances) for side, instances in sides.items()} == {
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"south": 30,
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"east": 52,
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"north": 48,
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"west": 59,
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}
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assert sum(item.startswith("vdd_pads\\[") for item in placed) == 24
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assert sum(item.startswith("vss_pads\\[") for item in placed) == 24
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assert sum(item.startswith("iovdd_pads\\[") for item in placed) == 16
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assert sum(item.startswith("iovss_pads\\[") for item in placed) == 16
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assert "u_extclk_i_pad.u_sg13g2_IOPadIn" in sides["south"]
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assert "u_gpio_31_io_pad.u_sg13g2_IOPadInOut4mA" in sides["east"]
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assert "u_sdram_dq15_io_pad.u_sg13g2_IOPadInOut4mA" in sides["west"]
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assert config["DIE_AREA"] == [0, 0, 8000, 8000]
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assert config["CORE_AREA"] == [365, 365, 7635, 7635]
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assert config["VDD_NETS"] == ["VDD", "IOVDD"]
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assert config["GND_NETS"] == ["VSS", "IOVSS"]
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assert set(config["MACROS"]) == {
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"RM_IHPSG13_1P_4096x16_c3_bm_bist",
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"RM_IHPSG13_1P_4096x8_c3_bm_bist",
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}
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assert len(config["PDN_MACRO_CONNECTIONS"]) == 6
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def test_chip_sdc_is_pad_aware_and_does_not_false_path_all_io(tmp_path: Path) -> None:
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module = load_module("retrosoc_librelane_sdc", FLOW_ROOT / "scripts/generate_sdc.py")
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arguments = SimpleNamespace(
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domains=DOMAINS,
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pin_map=PIN_MAP,
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ext_clk_hz=72_000_000,
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aud_clk_hz=18_432_000,
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have_pll=False,
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)
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sdc = module.render(arguments)
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assert "u_extclk_i_pad.u_sg13g2_IOPadIn/p2c" in sdc
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assert "u_usb2_ulpi_clk_i_pad.u_sg13g2_IOPadIn/p2c" in sdc
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assert "create_generated_clock -name clk_system" in sdc
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assert "set_clock_groups -name retrosoc_async -asynchronous" in sdc
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assert "set_input_delay -max" in sdc
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assert "set_output_delay -max" in sdc
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assert "set_false_path -from $reset_ext_rst_n_i_pad" in sdc
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assert "set_false_path -from [all_inputs]" not in sdc
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assert "set_false_path -to [all_outputs]" not in sdc
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def test_librelane_flow_is_single_level_chip_only() -> None:
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makefile = (FLOW_ROOT / "Makefile").read_text(encoding="utf-8")
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top_makefile = (ROOT / "Makefile").read_text(encoding="utf-8")
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lock = json.loads((ROOT / "dependencies/dependencies.lock.json").read_text())
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assert "librelane-chip:" in makefile
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assert "librelane-core" not in makefile
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assert "librelane-all" not in makefile
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assert "include physical/librelane/Makefile" in top_makefile
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ihp_filelist = (ROOT / "rtl/filelist/pdk_ihp130.fl").read_text(encoding="utf-8")
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assert ihp_filelist.index("sg13g2_udp.v") < ihp_filelist.index("sg13g2_stdcell.v")
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assert lock["sources"]["pdk_ihp130"]["revision"] == ("970a7688e7dcce2a6172797df9ef47bde2f60f9f")
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def test_bondpad_lef_matches_the_generated_master_contract() -> None:
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lef = (FLOW_ROOT / "bondpad/bondpad_70x70.lef").read_text(encoding="utf-8")
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assert "MACRO bondpad_70x70" in lef
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assert "CLASS COVER" in lef
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assert "SIZE 70.0 BY 70.0" in lef
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assert "SITE sg13g2_ioSite" in lef
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