mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
a64526c6a9
Implement SPI-P1 from docs/ip/spi.md with a PCLK master, registered APB responses, packed 8x32 TX/RX FIFOs, finite quotas and retained-session abort/recovery. Add the handwritten SVH/C register mirror and private source, credit and GPIO qualification interfaces. Add independent pin timing and data checks, malformed-waveform negatives, FIFO stall/resume and phase-safe abort cases. Provide isolated lint, simulation, compositional formal, synthesis, netlist and observational STA flows with source-bound artifacts and tool-component fingerprints. Validation on the reviewed worktree: 2085 pytest tests passed and one optional pypdf test skipped; both RTL simulators, fresh depth-192 BMC and cover, and ICS55/IHP130 block synthesis and netlist simulation passed. Formatting, style/readiness, Ruff and regression dry-runs passed. SPI remains outside product filelists with DMA capability disabled. SPI-P2/P3 integration, full-product regression closure and physical/IO qualification remain pending; no phase acceptance or policy change.
98 lines
3.2 KiB
Systemverilog
98 lines
3.2 KiB
Systemverilog
// One finite frame, exclusively clocked by PCLK. Abort never samples more bits.
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module spi_phase_ctrl (
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input logic clk_i,
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rst_n_i,
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start_i,
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abort_i,
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clamp_i,
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input logic cpol_i,
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cpha_i,
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lsb_first_i,
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frame16_i,
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input logic [15:0] divider_i,
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tx_data_i,
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input logic miso_i,
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output logic active_o,
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done_o,
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sck_o,
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mosi_o,
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output logic [15:0] rx_data_o
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);
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typedef struct packed {
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logic active, sck, mosi;
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logic [15:0] timer, tx_data, rx_data;
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logic [5:0] edge_count;
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} phase_t;
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phase_t s_phase_d, s_phase_q;
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logic [3:0] s_bit;
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logic [3:0] s_next_bit;
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logic [4:0] s_last_bit;
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logic s_trailing;
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assign s_last_bit = frame16_i ? 5'd15 : 5'd7;
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assign s_trailing = s_phase_q.edge_count[0];
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assign s_bit = lsb_first_i ? s_phase_q.edge_count[4:1] :
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4'(s_last_bit - s_phase_q.edge_count[5:1]);
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assign s_next_bit = lsb_first_i ? s_bit[3:0] + 4'd1 : s_bit[3:0] - 4'd1;
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assign active_o = s_phase_q.active;
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assign sck_o = clamp_i ? cpol_i : s_phase_q.sck;
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assign mosi_o = s_phase_q.mosi;
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always_comb begin
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s_phase_d = s_phase_q;
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done_o = 1'b0;
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rx_data_o = s_phase_q.rx_data;
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if (clamp_i) begin
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s_phase_d.active = 1'b0;
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s_phase_d.sck = cpol_i;
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end else if (!s_phase_q.active) begin
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s_phase_d.sck = cpol_i;
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if (start_i && !abort_i) begin
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s_phase_d.active = 1'b1;
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s_phase_d.edge_count = '0;
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s_phase_d.timer = divider_i - 16'd1;
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s_phase_d.tx_data = tx_data_i;
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s_phase_d.rx_data = '0;
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s_phase_d.mosi = cpha_i ? 1'b0 : tx_data_i[lsb_first_i?4'd0 : s_last_bit[3:0]];
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end
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end else if (abort_i && (s_phase_q.sck == cpol_i)) begin
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s_phase_d.active = 1'b0;
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end else if (s_phase_q.timer != 16'd0) begin
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s_phase_d.timer = s_phase_q.timer - 16'd1;
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end else if (abort_i) begin
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s_phase_d.sck = cpol_i;
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s_phase_d.active = 1'b0;
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end else begin
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s_phase_d.timer = divider_i - 16'd1;
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s_phase_d.sck = !s_phase_q.sck;
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s_phase_d.edge_count = s_phase_q.edge_count + 6'd1;
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if (s_trailing == cpha_i) begin
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s_phase_d.rx_data[s_bit[3:0]] = miso_i;
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rx_data_o[s_bit[3:0]] = miso_i;
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end
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if (cpha_i && !s_trailing) s_phase_d.mosi = s_phase_q.tx_data[s_bit[3:0]];
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if (!cpha_i && s_trailing && (s_phase_q.edge_count != {s_last_bit, 1'b1}))
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s_phase_d.mosi = s_phase_q.tx_data[s_next_bit[3:0]];
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if (s_phase_q.edge_count == {s_last_bit, 1'b1}) begin
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done_o = 1'b1;
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s_phase_d.active = 1'b0;
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end
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end
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end
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dffr #(
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.DATA_WIDTH($bits(phase_t))
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) u_phase (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_phase_d),
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.dat_o (s_phase_q)
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);
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`ifdef FORMAL
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// Reachable timer/edge invariants strengthen induction without constraining the environment.
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always_ff @(posedge clk_i) begin
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if (rst_n_i && s_phase_q.active) begin
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assert (s_phase_q.timer < divider_i);
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assert (s_phase_q.edge_count <= {s_last_bit, 1'b1});
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end
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end
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`endif
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endmodule
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