Implement SPI-P1 from docs/ip/spi.md with a PCLK master, registered APB
responses, packed 8x32 TX/RX FIFOs, finite quotas and retained-session
abort/recovery. Add the handwritten SVH/C register mirror and private
source, credit and GPIO qualification interfaces.
Add independent pin timing and data checks, malformed-waveform negatives,
FIFO stall/resume and phase-safe abort cases. Provide isolated lint,
simulation, compositional formal, synthesis, netlist and observational STA
flows with source-bound artifacts and tool-component fingerprints.
Validation on the reviewed worktree: 2085 pytest tests passed and one
optional pypdf test skipped; both RTL simulators, fresh depth-192 BMC and
cover, and ICS55/IHP130 block synthesis and netlist simulation passed.
Formatting, style/readiness, Ruff and regression dry-runs passed.
SPI remains outside product filelists with DMA capability disabled.
SPI-P2/P3 integration, full-product regression closure and physical/IO
qualification remain pending; no phase acceptance or policy change.
Document the P10 workload, profile selection, exact command matrix,
single-execution policy and retained source/binary identities. Record
matched performance, camera/audio/backend results, P7 and VGA follow-ups,
and the approved quality repairs with their original phase attribution.
Preserve failed attempts and distinguish later successful checks from
historical evidence. Record 2031 passed / 1 skipped for the final Pytest
run, five firmware builds and four byte-identical Tiny HEX comparisons.
Keep phase_accepted=false. Full long Icarus and complete supported
regression, publication/PDF readiness and final physical/PVT/board/sensor
qualification remain open; observed timing is not timing closure.
Validation: documentation links and commands checked; git diff --check
passes. The existing evidence remains bound to its pre-commit revision.
Follow the shared PSRAM model path and bind the DVP DMA selector together
with its Tiny/Mini definition, preserving Mini bulk-channel semantics.
Describe the 129-bit configuration/epoch CDC packet, 128-bit payload
extraction and applied register using the existing RTL. Complete isolated
fixture dependencies and add negative checks for channel, width, slice
and register-bypass drift without relaxing source validation.
The final publication selection passes 163 tests with one optional skip;
the full final worktree passes 2031 tests with the same pypdf skip.
Retain publication identity and strict source-drift checks. No RTL, PDF
generation, source-baseline refresh or physical qualification is included.
Require the implemented DVP-inclusive 0x7fff target set in the P7
acceptance image. Preserve the exact startup comparison and keep the
architectural allowed mask separate from implemented capabilities.
Add cross-source checks against the real SYSCTRL instance and negative
cases for stale, expanded, missing, ambiguous or weakened expectations.
Production capability bits and the HAL ABI are unchanged.
The focused 14-test selection and both ICS55/IHP130 P7 Verilator runs
pass strict Tiny terminal, lifecycle and profile checks. The final
worktree also passes 2031 Pytest tests with one optional pypdf skip.
Add an isolated SAFE24 QVGA capture, CPU statistics and SDIO save/readback
image with passive transaction observers. Keep ordinary images, production
RTL, public interfaces and dependency versions unchanged.
Retain matched binaries and source-bound stage evidence, distinguish
software comparisons from architectural measurements, and reject invalid
terminal results or incompatible resume inputs. Count SDIO descriptors and
status writebacks separately from pixel payload.
Validation on the final worktree includes 2031 passed / 1 skipped Pytest
tests, C format/policy/host checks, and directed observer tests on Icarus
and Verilator. Selected ICS55 and IHP130 SAFE24 campaigns and compact
backend checks pass; negative STA and warning observations are retained.
Complete P10 acceptance remains pending final regression and human review.
Specification: docs/ip/tiny-soc.md, TINY-R2-P10.
Remove one final LF from four Make files to satisfy the existing mbake
1.4.6 configuration. Preserve all other bytes and keep the independent
P10 implementation out of this formatting commit.
Final-worktree validation confirms identical configuration and command
expansion for five firmware variants, including the Mini lint dry-run.
Format, software policy and host checks pass. The existing editorconfig
newline discrepancy remains a separate policy issue.
Document the DVP integration contract, reviewed remediation and source-bound
ICS55/IHP130 evidence, preserving original phase IDs and historical runs.
Record matched firmware binaries, current functional results, observational
STA, warning deltas and unresolved global quality/qualification gaps.
Evidence was produced from 39ae718 plus the archived worktree; retain that
provenance rather than relabeling earlier runs with new commit identities.
P9 human acceptance remains pending. This documentation does not advance P10
or qualify a physical operating point.
Validation: read-only artifact/source hash review and git diff --check.
Add isolated default and camera LibreLane IO profiles, assigning camera
inputs to the pixel clock and keeping ordinary GPIO constraints in default.
Separate generated output roots and synchronize the commercial clock-domain
inventory with the P9 DVP domain.
Retained validation: nine LibreLane scenario tests and 50 commercial-flow/
Tiny reset-inventory tests pass. Constraints retain development assumptions;
no commercial EDA, physical signoff or board timing qualification is claimed.
Specification: docs/ip/tiny-soc.md, TINY-R2-P9.
Connect DVP to Tiny DMA2/request 11, IRQ15 and the camera pad/reset lifecycle.
Harden shared capture CDC, frame statistics, per-row size validation and HAL
cleanup while preserving the Mini DMA3 binding and existing register ABI.
Add deterministic capture/recovery firmware, source-bound evidence tooling,
focused RTL/host tests and compact netlist acceptance. Preserve SAFE24,
128 KiB main SRAM, private Crypto storage and the locked dependencies.
Retained validation: focused RTL, host/policy checks, Mini firmware, and
ICS55/IHP130 RECOVERY, QVGA, synthesis and boot/DVP netlist checks pass.
Full-system VGA remains historical; long full Icarus and broad regressions
remain deferred. Global publication/format gaps and negative observational
STA are retained, not reported as passing qualification.
Specification: docs/ip/tiny-soc.md, TINY-R2-P9.
Evidence: docs/ip/tiny-soc-verification.md.
Present the complete error bundle on the event sampling edge and clear stale
address and PC fields for rejected requests and polling timeouts. Preserve
register encodings, response latency and first-error snapshot semantics.
Add 12 error/IRQ scenarios for Tiny Icarus, Tiny Verilator and the Mini
Verilator consumer. Retained P9 validation covers these paths; see
docs/ip/tiny-soc-verification.md and docs/ip/xpi.md.
Document the optional NSS1 PSRAM contract, workload and evidence policy, P7 acceptance boundary, P8 correction follow-up, and profile-specific synthesis, netlist and observational STA results. Keep full Icarus, physical qualification and human P8 acceptance explicitly open.
Document the RCU ownership, profile/PDK mapping, exact validation commands,
matched firmware, source snapshots and current 06-00 backend evidence.
Separate historical checkpoints and the rejected 04-00 candidate from
current response-conservation and source-reset validation.
State the production DMA drain and common XPI reset preconditions without
claiming unrestricted standalone bridge source-reset support. Record the
54-case directed result, expected-negative checks and unchanged design
inputs that justify retaining the original backend evidence.
Preserve full-suite failures and focused corrections, interrupted Icarus
attempts, final-phase deferral, negative timing and missing physical
qualification. Keep P7 human acceptance and later phases separate.
Integrate the Tiny RCU, normalized REF24 control, external-input profiles,
single PLL backend, SYS/MEM/PCLK clocks, CPU-only WFI gating, peripheral
lifecycle control and retained debug behavior. Keep CPU and all 32 main
SRAM macros on SYS and the six private Crypto macros on PCLK.
Add the handwritten RCU register/HAL contract, RS_EBUSY, bounded SDK
operations and focused firmware. Preserve shared-IP defaults and the
ICS55/PLL SAFE24 boot and explicit IHP130/no-PLL compatibility profiles.
Use APB/AXI domain bridges and source-owned response holders to preserve
backpressured responses, complete aborted bursts and prevent stale replay.
Verify production DMA source-reset drain and common XPI endpoint reset
with extracted integration bindings and an independent scoreboard.
Add source-bound macro/clock audits, SAFE24 observational STA constraints
and commercial-adapter host checks. No P8 functionality or operating-point
qualification is included. See TINY-R2-P7 in docs/ip/tiny-soc.md.
Validation: 54 P7 directed tests pass, including both simulators, ten
source-reset ratio runs and two expected-negative drain mutations.
RTL format/style, clock/reset inventory, Ruff and both Tiny PDK PR dry-runs
pass. Retained 06-00 synthesis and strict netlist boots pass for both PDKs;
STA remains negative and observational. Source comparison confirms only
the follow-up tests changed after that backend campaign.
Evidence: build/ics55-tiny-2026-10-14-06-00-ff4b5cef6eb5/meta/
tiny-r2-p7-source-reset/summary.json. Earlier firmware, HAL and compatibility
results and the non-clean full-suite attempt retain their original
attribution. Full Icarus firmware is deferred to final Tiny qualification;
this commit does not constitute human phase acceptance or physical signoff.
Record parent and child process IDs for diagnostics, persist interruption
before cleanup, and ignore repeated termination signals during cleanup.
Close unexpected failures with a terminal result and retain the child's
exit status without treating namespace-local PID absence as completion.
Require a successful terminal run_flow result when checking simulation
logs with an associated result file. Cover repeated cancellation and
reject running, failed or inconsistent terminal records despite PASS text.
This supports the TINY-R2-P7 campaign. Interrupted and timed-out runs remain
non-acceptance evidence; UART output alone cannot qualify a Tiny simulation.
Advance the approved PWM dependency to
38efaf5e20f084a00148920087c60cadab61839b so Tiny RCU can publish the
committed PCLK rate through the existing PWM register interface.
Keep the static-clock default for existing consumers.
Required by TINY-R2-P7 in docs/ip/tiny-soc.md. The locked checkout and
P7 validation use this exact revision; dependency-lock validation passes.
Record the shared-IP and eight-channel DMA integration, common I2S/SDIO correctness fixes, deterministic workloads, snapshot update scopes and both PDKs' functional and smoke-flow evidence.
Keep original failed attempts, publication history and source attribution intact. The later final full Pytest passed 1726 tests with one optional pypdf skip in 4021.61 seconds, exit 0, in terminal session 36439; it has no standalone verdict log or JSON. Existing campaign evidence is not rewritten by this documentation commit.
Retain explicit negative timing, warning observations, legacy package/floorplan limits and pending physical qualification. Human phase acceptance and any P7 work remain separate.
Integrate RNG, CRC, WS2812, Crypto, I2S master and the SDIO private AXI owner on SAFE24. Preserve the 128 KiB main SRAM and six private Crypto macros, add product-specific DMA assignments and reject unsupported SDK operations.
Correct APB read strobes, I2S receive assembly and SDIO command timing, backpressure and descriptor retirement. Add pin-level workloads, source-bound evidence checks and publication/commercial consumer compatibility.
Validation of the final P6 worktree: 1726 pytest tests passed with one optional pypdf skip (exit 0, 4021.61 seconds; terminal session 36439). Both PDKs passed both RTL simulators, netlist boot and 38-macro binding checks. Shared formal, Mini compatibility and software/source quality gates passed.
Evidence remains attributed to the retained dirty-worktree snapshots based on b3b30a72cd under build/ics55-tiny-2026-10-12-11-50-2eb98c0e1fae/meta/tiny-r2-p6/. Timing is negative and warning observations are not promoted. This commit does not accept P6, qualify physical operation or enable P7.
Document corrected reset behavior, source-bound evidence, validation commands and both PDK timing observations. Mark the earlier reset repair as superseded while preserving its historical attribution.
Retain explicit limits for workload replay, full-function netlist testing and physical qualification. Human phase acceptance and P6 execution remain separate.
Drain remaining write beats before returning B, retain captured R/B responses, and append missing read error beats through the response spills. Preserve first-error attribution and prevent replay after target reset release.
Cover 28 reset scenarios in both simulators, including production DMA drain and APB bridge cases. Extend reset formal checks and publication contract mutation tests.
Validation: 101 focused tests passed; full Pytest reported 1685 passed and one optional pypdf skip. TINY ICS55 and IHP130 PR regressions passed. Timing remains observational and unclosed; no performance or physical qualification is claimed.
- Introduced for formal verification of fault handling in the Tiny R2 P5 architecture.
- Added to test target reset isolation and ensure proper handling of reset signals across multiple targets.
- Created to validate system-level interactions, including CPU and DMA progress during resets.
- Enhanced to include fault counting and master tracking for concurrent fault events.
- Developed to automate testing of concurrency, fault accounting, and retained-image acceptance.
- Updated Python test suite to validate new configurations and ensure proper integration with Tiny R2 P5 architecture.
- Updated SRAM instance paths in to reflect new hierarchy.
- Enhanced to include additional source files and updated parameterized tests for SRAM configurations.
- Modified to align with new SRAM structure and added a test for stale macro hierarchy.
- Introduced to validate dual-port local-memory protocol and CPU debug/reset functionality, including comprehensive simulation checks.
- Implemented tests for WS2812 DMA sessions and refill functionality in .
- Added a new RTL testbench for WS2812 refill functionality in .
- Enhanced AXI4 data crossbar testbench to diagnose MMIO boundaries for the Mini DMA.
- Created a new Python test suite for Tiny R2 P3 to validate firmware warnings and layout placements.
- Updated existing WS2812 tests to parameterize and check for DMA backpressure integration.
- Added support for optional files in GDS generation to handle legacy layouts.
- Introduced macro-level LVS/ERC processing to improve verification of hard macros.
- Updated STA scripts to adopt PrimeTime analysis settings from legacy flows.
- Enhanced synthesis settings to align with CX55 legacy flow, including clock gating and area optimization.
- Improved reporting functions to include detailed synthesis summaries and area metrics.
- Updated package generation script to support both TINY and MINI SOC configurations.
- Added comprehensive tests for ECO translation, timing contract generation, and constraint handling.
- Ensured compatibility with new timing contract formats and enhanced error handling for domain drift.
- Updated to include support for the ICS55 PDK, allowing for conditional source inputs and configuration checks.
- Added new test cases for the ICS55 platform, including PLL backend and GPIO readback functionality.
- Modified existing tests to accommodate changes in configuration and source input handling.
- Introduced new parameters in the testbench for better configurability.
- Ensured compatibility checks for the IHP130 and ICS55 PDKs in the feasibility script.
- Enhanced the publication tests to validate hardware changes more robustly.
- Updated tiny-soc.md to reflect the 2026-10-07 refreeze, establishing ICS55 as the default target PDK with HAVE_PLL=YES.
- Added detailed sections on final timing gate policies, PLL integration, and execution order for Tiny SoC.
- Modified soc-family-positioning.md to indicate the new default target for Tiny as ICS55/PLL while maintaining IHP130 compatibility.
- Enhanced pdk/README.md and setup.py to support the integration of the locked ICS55 PLL views, including setup commands and validation.
- Introduced tests for the ICS55 PLL dependency to ensure proper integration and validation of PLL views.
- Updated rtl/tiny/README.md to clarify the current executable baseline and the pending integration of ICS55.
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads.
- Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves.
- Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements.
- Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts.
- Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
- Introduced a new test file to validate the functionality of the Tiny baseline evidence.
- Implemented tests for CPU checksum verification, log parsing, error handling, and artifact identity checks.
- Added parameterized tests to cover various edge cases, including handling of incomplete or duplicate measurements and incorrect data.
- Ensured that the tests validate the integrity of simulation results and the retention of compiler commands after post-processing.
- Introduced the PPALite extension, approved on 2026-10-05, detailing its features such as camera-inline Y extraction, RGB565 ordering, and fixed pixel/line sampling.
- Updated the tiny-soc-verification and tiny-soc documentation to reflect the new PPALite extension, including its integration with existing DVP and DMA channels.
- Added comprehensive evidence tables for PPALite phases (PPALITE-P0 to P5) outlining required evidence and current statuses.
- Clarified the relationship between PPALite and existing SPI/PIO extensions, emphasizing that earlier results cannot qualify newly added PPALite logic.
- Enhanced the README files in the RTL directory to specify PPALite's role and requirements in the context of Tiny SoC development.
- Introduced the separately approved SPI extension (2026-10-04) for the Tiny SoC, detailing the addition of SPI0 as a master-only controller with 8/16-bit capabilities.
- Updated documentation to reflect the SPI phases (SPI-P0 to SPI-P5) and their respective requirements, including DMA V2.2 pacing and fixed-MMIO requests.
- Specified GPIO assignments for SPI functionality, including the use of previously reserved Gen1 ALT routes.
- Clarified the integration boundaries and dependencies on existing R2 and PIO-lite phases, emphasizing the need for complete implementation before qualification.
- Documented the implications of SPI integration on existing GPIO and DMA channels, ensuring no additional resources are allocated without proper validation.
- Updated the verification ledgers to track pending evidence and implementation gaps for both SPI and PIO-lite extensions.
- Updated the tiny-soc-verification.md to clarify the separation of PIO-lite as a standard-product extension, detailing its planned features and evidence requirements.
- Revised tiny-soc.md to emphasize the historical context of the R2 design freeze and the independent nature of the PIO-lite extension, including its integration requirements and phase structure.
- Added details in soc-family-positioning.md regarding the PIO-lite extension's capabilities and its distinction from the R2 performance-only approval.
- Enhanced README.md files in rtl/ip and rtl/tiny to reflect the future integration of the PIO-lite extension, specifying its features and the implications for existing RTL and DMA configurations.
- Clarified integration details for WS2812 and XPI in respective documentation.
- Updated the SOC family positioning to reflect changes in clock/reset configurations and DMA channels.
- Enhanced README files for librelane and RTL to include R2 target specifics, including execution order and peripheral contracts.
- Specified the active execution order for R2 and clarified the implications of the new architecture on performance and integration.
- Added details on the Tiny Gen1 target's shared XPI register/LUT/PHY contract and optional NSS1 PSRAM integration.
- Clarified the memory model to include optional initialized XPI NSS1 PSRAM for whole-frame data.
- Updated the edge I/O section to reflect the alternate DVP V2 camera profile and GPIO allocations.
- Revised the shared services and package specifications to align with the latest P10 refreeze.
- Enhanced the README to include P10 documentation refreeze details, emphasizing DVP V2 contract and PSRAM integration.
- Updated fault reference documentation to clarify Linux termination behavior and NPU-P6 requirements.
- Enhanced Linux runtime section with emphasis on platform setup and kernel handoff processes.
- Revised overview section to include detailed descriptions of NPU capabilities and memory configurations.
- Improved product use documentation to specify Linux rootfs behavior and acceptance checkpoints.
- Clarified reset summary to differentiate between Linux and smoke/NPU-P6 acceptance processes.
- Updated software section to reflect changes in Linux image loading and readiness protocols.
- Modified build scripts to support RV64 architecture and ensure proper ELF requirements.
- Enhanced NPU compiler to support cycle counting for RV64 and RV32 architectures.
- Added tests to validate new configurations and ensure compliance with updated publication contracts.
- Revised WS2812 documentation to clarify the shared block and integration details for Mini and Tiny targets.
- Enhanced PLL Dynamic Clock Control document to specify differences between Mini and Tiny RCU implementations.
- Updated SoC Family Positioning to reflect changes in the Gen1 product/package target, including shared IP and DMA details.
- Adjusted Tiny MCU Integration README to include new features and requirements for the 2026-09-30 P6 target, emphasizing the shared peripherals and clock specifications.
- Introduced a new maintenance reference for dependency and environment routing.
- Enhanced the feature implementation skill with migration references for behavior-preserving changes.
- Added regression and RTL migration references to support feature review processes.
- Created a new physical flow skill with detailed execution and recovery guidelines.
- Updated evals for feature implementation and review skills to include new scenarios.
- Improved the AGENTS.md and tests to reflect the new skills and references.
- Added new skills for retroSoC feature implementation and review, including YAML configurations and evaluation cases.
- Removed deprecated mini feature design and implementation skills.
- Updated documentation to reflect changes in skill names and functionalities.
- Adjusted test cases to ensure compatibility with the new skill structure and validate the presence of required files and metadata.
- Updated mailbox purpose tests to reflect new write order and sequence handling.
- Added tests to ensure Linux-ready values match LP contract and constants match Linux helper.
- Introduced tests to verify that offset changes do not hide stale Linux helpers.
- Enhanced environment tests to report current locked launcher and runtime versions.
- Added checks for SBT launcher presence in environment labels.
- Improved full diagram tests to validate storage geometry and RSA vector configurations.
- Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries.
- Modified script tools tests to include Vexii generation validation and updated workflow assertions.
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow.
- Added to create a checksummed delivery archive for the Tiny LibreLane implementation.
- Created for synthesis-only header of the locked IHP SRAM macro physical views.
- Implemented to limit OpenSTA report enumeration for path counts.
- Updated to include power pad definitions.
- Enhanced to handle power pad counts and validation.
- Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
- Added build_hp_rtthread.py for building the RT-Thread kernel with RV64 support.
- Updated build_hp_smoke.py to target RV64 architecture and modified output filenames.
- Modified generate_vexiiriscv.py to reflect RV64 configuration and memory management.
- Created hp_tools.py for shared utilities related to RV64 builds.
- Enhanced package_hp_boot.py to package RV64 workloads and updated versioning.
- Implemented run_hp_sim.py for executing and validating HP workloads with specific markers.
- Developed setup_hp_rtthread.py for installing RT-Thread source and environment setup.
- Updated GenerateRetroSocHp.scala to generate RV64 application cores.
- Enhanced tests for HP boot bundles, platform specifications, and tool utilities to accommodate RV64 changes.
- Adjusted test cases to validate new workload types and ensure compatibility with RV64 architecture.
- Updated test paths in to point to the new directory structure for crypto files.
- Introduced to validate firmware identity and reject stale firmware based on source changes and simulation logs.
- Enhanced to include additional memory status and control registers, ensuring alignment with RTL definitions.
- Introduced new Tiny Gen1 datasheet with waveform rendering capabilities.
- Implemented example functions for various peripherals including archinfo, clint, dma, gpio, i2c, pwm, rtc, sram, sysctrl, timer, uart, wdg, and xpi.
- Enhanced register reference parsing to accommodate Tiny-specific memory maps.
- Created a dedicated Tiny reference module to isolate Tiny publications from Mini inputs.
- Developed comprehensive tests to validate Tiny publication configurations, register inventories, and evidence claims.
- Updated RTL documentation to reflect the separation of Tiny and Mini product lines.
- Updated paths in test files to reflect new directory structure for RTL and script files.
- Changed references from rtl/mini to rtl/ip and scripts/rtl where applicable.
- Added a new test file for Tiny product isolation, ensuring independent ABI and bus acceptance.
- Enhanced tests for memory map generation and protocol contracts for Tiny architecture.
- Ensured that all tests are aligned with the latest directory structure and naming conventions.
- Introduced for independent mathematical operations and RSA fixtures.
- Implemented for testing DMA channels with AES ECB and memory interactions.
- Created to validate RSA-2048 operations and Montgomery reduction.
- Developed for testing AES and SHA vector compliance.
- Added to validate image packing, integer root calculations, and inventory checks.
- Ensured robust error handling and validation in tests to catch data corruption and recursive hierarchy issues.
- Clarified P5 capabilities including direct/ring WAV/FLAC jobs and new KWS model integration.
- Specified requirements for evidence acceptance related to P5 enhancements.
- Noted that P6 MP3 support remains deferred with emphasis on design requirements.
- Updated details on P9 refreeze requirements, including macro-backed storage and future obligations.
- Reinforced that existing system clock/reset/IRQ/resource assignments remain unchanged.
- Updated the JPEG table register bank module to use combinational logic for data handling and simplified the write logic for quantization, DC, and AC entries.
- Introduced a new function in the run_flow script to handle process termination more gracefully, including signal handling for interrupts.
- Enhanced the flow script to log peak RSS memory usage during execution.
- Modified multiple testbench files to include new storage access signals and improved the test logic for better validation of KWS and SRAM interactions.
- Updated tests to validate the new peak RSS memory logging in the flow script.
- Adjusted Yosys synthesis recipes to include timeout settings and ensure proper reporting of pre-memory synthesis outputs.
- Introduced to define the development environment and validate runtime/platform contracts.
- Enhanced with to ensure change markers adhere to publication rules.
- Updated to integrate boot acceptance checks and ensure dependencies are correctly managed.
- Added tests for environment validation, publication change scope, and CI stages to prevent regression and ensure compliance with publication standards.
- Implemented checks in to validate the presence of development environment dependencies.
- Refactored existing tests to improve coverage and ensure accurate validation of publication claims and software configurations.
- Modified waveforms.json to reflect changes in resource tracking from nine to ten positions for both resource-controller integration and reference monitor parameters.
- Enhanced dev_reference.py to include NPU sources and updated CI snapshot validation to accommodate new statuses and conclusions.
- Added example NPU implementation in npu.c for job submission and result handling.
- Updated format_reference.py to validate NPU descriptor word offsets against RTL definitions.
- Adjusted storage_reference.py to reflect changes in APU and NPU local memory configurations.
- Enhanced system_reference.py to include NPU implementation details and validate accelerator claims.
- Updated tests to reflect changes in the structure and coverage of NPU and APU components, ensuring accurate validation of configurations and claims.
- Introduced new tests in v05.py to ensure distinct handling of executable configurations and evidence for NPU and APU.
- Introduced for deterministic corpus framing, CRC checks, and regression evidence for NPU-P6.
- Added to validate NPU-P6 reference execution.
- Created a new RTL model for gate-level NPU transactions.
- Updated to instantiate and streamline the testbench.
- Enhanced with capability checks and added NPU-P6 reference contract tests.
- Modified to include in the source list and refactor rejection logic.
- Updated README.md to document new test scripts and their purposes.
- Introduced differential tests for the APU-P7 frontend profile-1 BAM to ensure consistency with ROM and generator outputs.
- Implemented concurrent decode and continuous KWS smoke tests for APU-P7 to validate system stability under load.
- Added accuracy qualification tests for APU-P7 to verify through-hardware performance against expected results.
- Created contention tests for APU-P8 to assess USB2/SDIO0/APU Gateway A interactions.
- Developed quiesced loader admission tests for APU-P8 to ensure proper handling of DMA operations.
- Added post-fault visibility tests for APU-P8 HP interconnect to confirm fault handling capabilities.
- Enhanced register parity tests to include ABI digest verification for consistency across implementations.
- Updated publication register tests to reflect changes in capability constants for P5 and P7 profiles.
- Removed unsupported fault handling from and replaced it with a test for average pooling execution.
- Updated the test for unsupported placements to validate average pooling and depthwise convolution placements.
- Introduced new tests for softmax functionality in , including parameter validation and edge cases.
- Added qualification tests to ensure rejection of common-mode numerical errors and incomplete runs in .
- Enhanced RTL tests to cover memory downsizing and kernel burst capabilities in and .
- Adjusted boot status assertions in to reflect updated expected values.
This commit includes new shell source files for the NPU, specifically:
- npu_mac_array.sv
- npu_accumulator.sv
- npu_vector.sv
- npu_requantizer.sv
These additions aim to improve the testing coverage and functionality of the NPU RTL shell.
- Introduced scoped typography rules for compact cells and emphasized labels in the SoC functional overview.
- Updated the diagram to utilize new typography settings, including size adjustments for CDC and Gateway labels.
- Implemented geometry validation for SoC diagrams to ensure proper routing and clearance between elements.
- Added comprehensive tests for geometry validation, PDF typography checks, and compact text handling.
- Created new Python modules for shared geometry and PDF-bound typography checks to streamline validation processes.
- Enhanced documentation to clarify typography requirements and routing styles for SoC diagrams.
- Added validation checks for GA2D soft reset and error handling in .
- Improved resource controller tests in to cover IRQ routing and ownership scenarios.
- Updated performance log tests in to reflect changes in GA2D features and formats.
- Introduced a new netlist transaction test for GA2D in to ensure synthesized block functionality.
- Modified publication software tests in to account for new GA2D stages.
- Adjusted script tools tests in for updated configuration values.
- Added print statements for better traceability in GA2D reference campaign tests.
maksyuki