mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
a64526c6a9
Implement SPI-P1 from docs/ip/spi.md with a PCLK master, registered APB responses, packed 8x32 TX/RX FIFOs, finite quotas and retained-session abort/recovery. Add the handwritten SVH/C register mirror and private source, credit and GPIO qualification interfaces. Add independent pin timing and data checks, malformed-waveform negatives, FIFO stall/resume and phase-safe abort cases. Provide isolated lint, simulation, compositional formal, synthesis, netlist and observational STA flows with source-bound artifacts and tool-component fingerprints. Validation on the reviewed worktree: 2085 pytest tests passed and one optional pypdf test skipped; both RTL simulators, fresh depth-192 BMC and cover, and ICS55/IHP130 block synthesis and netlist simulation passed. Formatting, style/readiness, Ruff and regression dry-runs passed. SPI remains outside product filelists with DMA capability disabled. SPI-P2/P3 integration, full-product regression closure and physical/IO qualification remain pending; no phase acceptance or policy change.
224 lines
8.1 KiB
Systemverilog
224 lines
8.1 KiB
Systemverilog
module spi_formal (
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input wire clk_i
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);
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reg rst_n = 0;
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always @(posedge clk_i) rst_n <= 1;
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(* anyseq *) reg miso;
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`ifndef SPI_FORMAL_BOUNDED
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`ifndef SPI_FORMAL_REGISTER
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(* anyconst *) reg cpol, cpha, lsb, frame16;
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(* anyconst *) reg [15:0] divider;
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(* anyseq *) reg request_start, request_abort;
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(* anyseq *) reg [15:0] tx_data;
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wire active, done, sck, mosi;
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wire [15:0] rx_data;
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reg closing = 0;
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always @(posedge clk_i) begin
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assume (divider >= 1 && divider <= 4);
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if (!rst_n || !active) closing <= 0;
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else if (request_abort) closing <= 1;
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end
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spi_phase_ctrl u_phase (
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.clk_i (clk_i),
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.rst_n_i (rst_n),
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.start_i (request_start && !active),
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.abort_i (request_abort || closing),
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.clamp_i (!rst_n),
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.cpol_i (cpol),
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.cpha_i (cpha),
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.lsb_first_i(lsb),
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.frame16_i (frame16),
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.divider_i (divider),
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.tx_data_i (tx_data),
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.miso_i (miso),
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.active_o (active),
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.done_o (done),
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.sck_o (sck),
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.mosi_o (mosi),
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.rx_data_o (rx_data)
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);
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spi_formal_props u_properties (
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.clk_i (clk_i),
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.rst_n_i (rst_n),
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.active_i(active),
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.done_i (done),
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.abort_i (request_abort || closing),
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.sck_i (sck),
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.cpol_i (cpol)
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);
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`endif
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`endif
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`ifdef SPI_FORMAL_BOUNDED
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// Component contract: register legality/stability is proved separately.
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// All command values and legal FIFO service interleavings remain symbolic.
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spi_ctrl_if u_session ();
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reg [7:0] model_cycles = 0;
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always @(posedge clk_i) begin
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if (!rst_n) model_cycles <= 0;
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else if (model_cycles != 192) model_cycles <= model_cycles + 1;
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if (rst_n) cover (model_cycles == 192);
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end
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reg [4:0] session_cfg = 0;
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reg [3:0] segment_cfg = 0;
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reg [2:0] frame_count = 0;
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reg [2:0] period_value = 1;
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reg [1:0] setup_value = 1, hold_value = 1, inactive_value = 1;
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(* anyseq *)reg update_configuration;
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(* anyseq *)reg [4:0] next_session;
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(* anyseq *)reg [3:0] next_segment;
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(* anyseq *)reg [2:0] next_count;
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(* anyseq *) reg [1:0] next_period, next_setup, next_hold, next_inactive;
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(* anyseq *) reg [8:0] command_value;
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(* anyseq *) reg [1:0] fifo_access, pending_start;
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(* anyseq *) reg [3:0] transport;
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(* anyseq *) reg route_ok, gpio_ok, handback, dma_fault, credit_fault_value;
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(* anyseq *)reg apb_pending;
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(* anyseq *)reg [31:0] payload;
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spi_pkg::configuration_t model_cfg;
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spi_pkg::status_t model_status;
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wire [31:0] claim_mask;
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wire core_sck, core_mosi, core_cs, core_oe;
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assign claim_mask = (session_cfg[3] || session_cfg[4]) ? 32'hd8000000 : 32'h98000000;
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always @* begin
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model_cfg = '0;
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model_cfg.session = session_cfg;
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model_cfg.segment = segment_cfg;
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model_cfg.frames = {29'd0, frame_count};
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model_cfg.divider = {13'd0, period_value};
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model_cfg.setup_cycles = {14'd0, setup_value};
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model_cfg.hold_cycles = {14'd0, hold_value};
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model_cfg.inactive_cycles = {14'd0, inactive_value};
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model_cfg.dummy = 16'hffff;
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model_cfg.watermarks = 12'h100;
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end
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assign u_session.cfg = model_cfg;
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assign model_status = u_session.stat;
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assign u_session.cmd = command_value;
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assign u_session.tx_data = payload;
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assign u_session.tx_push = (fifo_access == 1) && u_session.tx_ready && command_value == 0;
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assign u_session.rx_pop = (fifo_access == 2) && u_session.rx_ready && command_value == 0;
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always @(posedge clk_i) begin
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assume (next_count <= 5);
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assume (next_session[4:3] != 2'b11);
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assume (next_segment[2:1] != 2'd3);
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assume (next_setup != 0 && next_hold != 0 && next_inactive != 0);
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if (!rst_n) begin
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session_cfg <= 0;
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segment_cfg <= 0;
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frame_count <= 0;
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period_value <= 1;
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setup_value <= 1;
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hold_value <= 1;
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inactive_value <= 1;
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end else if (update_configuration && command_value == 0) begin
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if (u_session.session_writable) begin
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session_cfg <= next_session;
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period_value <= {1'b0, next_period} + 3'd1;
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setup_value <= next_setup;
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hold_value <= next_hold;
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inactive_value <= next_inactive;
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end
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if (u_session.segment_writable) begin
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segment_cfg <= next_segment;
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if (next_count != 0) frame_count <= next_count;
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end
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end
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if (rst_n) begin
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assert (model_status.status[3:0] <= 8);
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if (!gpio_ok || !route_ok) assert (!core_oe);
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cover (core_oe && !core_cs && core_sck != $past(core_sck));
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cover (u_session.events[0]);
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cover (model_status.status[3:0] == 8);
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end
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end
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spi_master_core u_session_core (
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.apb_pending_i (apb_pending),
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.clk_i (clk_i),
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.rst_n_i (rst_n),
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.claim_i (claim_mask),
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.ready_pins_i (route_ok ? claim_mask : 32'd0),
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.gpio_ready_i (gpio_ok),
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.handback_i (handback),
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.dma_status_i (transport),
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.dma_start_pending_i(pending_start),
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.dma_error_i (dma_fault),
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.credit_fault_i (credit_fault_value),
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.miso_i (miso),
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.sck_o (core_sck),
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.mosi_o (core_mosi),
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.cs_n_o (core_cs),
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.output_enable_o (core_oe),
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.ctrl (u_session)
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);
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`endif
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`ifdef SPI_FORMAL_REGISTER
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apb4_if u_apb (
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.pclk (clk_i),
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.presetn(rst_n)
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);
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spi_ctrl_if u_ctrl ();
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(* anyseq *) reg [31:0] address_data, write_data, rx_data_value;
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(* anyseq *) reg selected, access_phase, writing, command_error;
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(* anyseq *)reg [1:0] ready_value;
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(* anyseq *)reg [5:0] event_value;
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(* anyseq *) reg [1:0] origin_value, credit_value, retire_value;
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(* anyseq *)reg [4:0] request_value;
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(* anyseq *)reg [2:0] channel_value;
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wire irq, credit_fault;
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wire fifo_pending;
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wire [1:0] committed;
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reg register_past_valid = 0;
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assign u_apb.paddr = address_data;
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assign u_apb.pwdata = write_data;
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assign u_apb.pstrb = 4'hf;
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assign u_apb.pprot = 0;
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assign u_apb.psel = selected;
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assign u_apb.penable = access_phase;
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assign u_apb.pwrite = writing;
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assign u_ctrl.stat = '0;
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assign u_ctrl.cmd_err = command_error;
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assign u_ctrl.session_writable = 1;
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assign u_ctrl.segment_writable = 1;
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assign u_ctrl.tx_ready = ready_value[0];
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assign u_ctrl.rx_ready = ready_value[1];
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assign u_ctrl.rx_data = rx_data_value;
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assign u_ctrl.events = event_value;
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assign u_ctrl.clear_events = 0;
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assign u_ctrl.clear_bindings = 0;
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spi_reg u_reg (
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.clk_i (clk_i),
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.rst_n_i (rst_n),
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.clock_hz_i (32'd24000000),
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.origin_i (origin_value),
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.request_i (request_value),
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.channel_i (channel_value),
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.credit_valid_i (credit_value),
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.credit_retire_i (retire_value),
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.dma_status_i (4'd0),
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.dma_start_pending_i(2'd0),
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.credit_commit_o (committed),
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.credit_pending_o (), // Observed through the wrapper in integration fixtures.
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.fifo_pending_o (fifo_pending),
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.credit_fault_o (credit_fault),
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.irq_o (irq),
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.apb4 (u_apb),
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.ctrl (u_ctrl)
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);
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always @(posedge clk_i) begin
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register_past_valid <= rst_n;
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if (rst_n && register_past_valid) begin
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if ($past(selected && access_phase)) assert (u_apb.pready);
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if ($past(u_ctrl.tx_push || u_ctrl.rx_pop)) assert (fifo_pending);
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if ($past(u_apb.pready)) begin
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assert (u_apb.prdata == $past(u_apb.prdata));
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assert (u_apb.pslverr == $past(u_apb.pslverr));
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end
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if (origin_value != 1) assert (committed == 0);
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if (u_apb.pready) begin
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assert (!u_ctrl.tx_push && !u_ctrl.rx_pop && u_ctrl.cmd == 0);
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end
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end
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end
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`endif
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endmodule
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