mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
a64526c6a9
Implement SPI-P1 from docs/ip/spi.md with a PCLK master, registered APB responses, packed 8x32 TX/RX FIFOs, finite quotas and retained-session abort/recovery. Add the handwritten SVH/C register mirror and private source, credit and GPIO qualification interfaces. Add independent pin timing and data checks, malformed-waveform negatives, FIFO stall/resume and phase-safe abort cases. Provide isolated lint, simulation, compositional formal, synthesis, netlist and observational STA flows with source-bound artifacts and tool-component fingerprints. Validation on the reviewed worktree: 2085 pytest tests passed and one optional pypdf test skipped; both RTL simulators, fresh depth-192 BMC and cover, and ICS55/IHP130 block synthesis and netlist simulation passed. Formatting, style/readiness, Ruff and regression dry-runs passed. SPI remains outside product filelists with DMA capability disabled. SPI-P2/P3 integration, full-product regression closure and physical/IO qualification remain pending; no phase acceptance or policy change.
93 lines
3.1 KiB
Systemverilog
93 lines
3.1 KiB
Systemverilog
`timescale 1ns / 1ps
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module spi_packer_tb;
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logic clk_i = 0, rst_n_i = 0, clear_i = 0, frame16_i = 0;
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logic [1:0] direction_i = 0;
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logic [31:0] quota_i = 10, tx_data_i = 0;
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logic tx_push_i = 0, rx_pop_i = 0, request_start = 0, frame_done_i = 0, last_frame_i = 0;
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logic [15:0] rx_frame_i = 0, tx_frame_o;
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logic [31:0] rx_data_o, tx_words_o, rx_words_o, rx_removed_o;
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logic tx_ready_o, rx_ready_o, tx_frame_ready_o, rx_frame_ready_o, empty_o;
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logic [3:0] tx_level_o, rx_level_o;
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always #20.833 clk_i = ~clk_i;
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spi_word_packer u_packer (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clear_i (clear_i),
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.frame16_i (frame16_i),
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.direction_i (direction_i),
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.quota_i (quota_i),
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.tx_data_i (tx_data_i),
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.tx_push_i (tx_push_i),
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.rx_pop_i (rx_pop_i),
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.frame_start_i (request_start && tx_frame_ready_o && rx_frame_ready_o),
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.frame_done_i (frame_done_i),
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.last_frame_i (last_frame_i),
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.rx_frame_i (rx_frame_i),
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.tx_frame_o (tx_frame_o),
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.rx_data_o (rx_data_o),
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.tx_words_o (tx_words_o),
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.rx_words_o (rx_words_o),
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.rx_removed_o (rx_removed_o),
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.tx_ready_o (tx_ready_o),
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.rx_ready_o (rx_ready_o),
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.tx_frame_ready_o(tx_frame_ready_o),
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.rx_frame_ready_o(rx_frame_ready_o),
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.empty_o (empty_o),
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.tx_level_o (tx_level_o),
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.rx_level_o (rx_level_o)
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);
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initial begin
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repeat (3) @(negedge clk_i);
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rst_n_i = 1;
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for (integer index = 0; index < 8; index++) begin
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tx_push_i = 1;
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tx_data_i = 32'(index);
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@(negedge clk_i);
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end
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if (tx_level_o != 8 || tx_ready_o) $fatal(1, "SPI full FIFO eligibility");
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request_start = 1;
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tx_push_i = 1;
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@(negedge clk_i);
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request_start = 0;
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tx_push_i = 0;
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if (tx_level_o != 7 || tx_words_o != 8) $fatal(1, "SPI full lookahead admitted extra word");
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clear_i = 1;
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@(negedge clk_i);
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clear_i = 0;
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request_start = 1;
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tx_push_i = 1;
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if (tx_frame_ready_o) $fatal(1, "SPI empty fallthrough");
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@(negedge clk_i);
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request_start = 0;
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tx_push_i = 0;
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if (tx_level_o != 1 || tx_words_o != 1) $fatal(1, "SPI empty simultaneous push/pop");
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clear_i = 1;
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@(negedge clk_i);
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clear_i = 0;
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direction_i = 2;
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frame16_i = 1;
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for (integer frame = 0; frame < 16; frame++) begin
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request_start = 1;
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@(negedge clk_i);
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request_start = 0;
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frame_done_i = 1;
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rx_frame_i = 16'(frame);
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@(negedge clk_i);
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frame_done_i = 0;
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end
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if (rx_level_o != 8 || rx_frame_ready_o) $fatal(1, "SPI RX reservation at full");
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request_start = 1;
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rx_pop_i = 1;
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@(negedge clk_i);
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request_start = 0;
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rx_pop_i = 0;
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if (rx_level_o != 7 || rx_words_o != 8 || rx_removed_o != 1) $fatal(1, "SPI RX full pop");
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$display("SPI_P1_PASS spi_packer_tb");
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$finish;
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end
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initial begin
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#100000;
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$fatal(1, "SIM_TEST_TIMEOUT SPI packer");
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end
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endmodule
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