mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
a64526c6a9
Implement SPI-P1 from docs/ip/spi.md with a PCLK master, registered APB responses, packed 8x32 TX/RX FIFOs, finite quotas and retained-session abort/recovery. Add the handwritten SVH/C register mirror and private source, credit and GPIO qualification interfaces. Add independent pin timing and data checks, malformed-waveform negatives, FIFO stall/resume and phase-safe abort cases. Provide isolated lint, simulation, compositional formal, synthesis, netlist and observational STA flows with source-bound artifacts and tool-component fingerprints. Validation on the reviewed worktree: 2085 pytest tests passed and one optional pypdf test skipped; both RTL simulators, fresh depth-192 BMC and cover, and ICS55/IHP130 block synthesis and netlist simulation passed. Formatting, style/readiness, Ruff and regression dry-runs passed. SPI remains outside product filelists with DMA capability disabled. SPI-P2/P3 integration, full-product regression closure and physical/IO qualification remain pending; no phase acceptance or policy change.
120 lines
4.4 KiB
Systemverilog
120 lines
4.4 KiB
Systemverilog
// Pin-only oracle: no DUT state/shifter references. Timing is counted in PCLKs.
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// Fault bits: 0 half-period, 1 CS setup, 2 first-bit setup, 3 incomplete frame,
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// 4 CS hold, 5 CS inactive, 6 edge after abort, 7 pause polarity, 8 payload.
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// Normal fixtures must fail on any fault; the checker fixture tests rejection.
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module spi_pin_bfm (
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input logic [15:0] divider_i,
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setup_i,
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hold_i,
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inactive_i,
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input logic segment_i,
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pause_i,
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input logic [15:0] dummy_i,
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input logic clk_i,
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begin_i,
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enabled_i,
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abort_i,
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input logic cpol_i,
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cpha_i,
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lsb_i,
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frame16_i,
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input logic [ 1:0] direction_i,
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input logic cs_n_i,
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sck_i,
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mosi_i,
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output logic miso_o,
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output integer frames_o,
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edges_o,
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output logic [ 8:0] faults_o
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);
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logic previous_sck = 0;
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logic [15:0] received = 0;
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integer samples = 0;
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integer index_bit;
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integer width_bits;
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logic [31:0] expected_word;
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logic [15:0] expected_frame, response;
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integer cycle = 0, last_edge = 0, segment_start = 0, released = 0;
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integer frame_edges = 0;
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logic previous_cs = 1, previous_mosi = 0;
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logic have_edge = 0, have_release = 0, aborted = 0;
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function automatic logic [15:0] reply(input integer frame);
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return 16'ha5c3 ^ (16'(frame) * 16'h1237);
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endfunction
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always @(negedge clk_i) begin
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width_bits = frame16_i ? 16 : 8;
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if (begin_i) begin
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cycle = 0;
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last_edge = 0;
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segment_start = 0;
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released = 0;
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frame_edges = 0;
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have_edge = 0;
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have_release = 0;
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aborted = 0;
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faults_o = 0;
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previous_cs = cs_n_i;
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previous_mosi = mosi_i;
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frames_o = 0;
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edges_o = 0;
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samples = 0;
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received = 0;
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previous_sck = cpol_i;
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response = reply(0);
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miso_o = response[lsb_i?0 : width_bits-1];
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end else if (enabled_i) begin
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cycle++;
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if (segment_i || (previous_cs && !cs_n_i)) segment_start = cycle;
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if (abort_i) aborted = 1;
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if (previous_cs && !cs_n_i && have_release && cycle - released < integer'(inactive_i))
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faults_o[5] = 1;
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if (!previous_cs && cs_n_i) begin
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if (sck_i != cpol_i || (!aborted && frame_edges != 0)) faults_o[3] = 1;
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if (have_edge && cycle - last_edge < integer'(hold_i)) faults_o[4] = 1;
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have_release = 1;
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released = cycle;
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end
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if (pause_i && (!cs_n_i && sck_i != cpol_i)) faults_o[7] = 1;
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if (!cs_n_i && sck_i != previous_sck) begin
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if (have_edge) begin
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// Only the idle CPOL interval BETWEEN complete frames may stretch.
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if (cycle - last_edge < integer'(divider_i) ||
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((frame_edges != 0) && cycle - last_edge != integer'(divider_i)))
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faults_o[0] = 1;
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end
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if (aborted && (previous_sck == cpol_i || sck_i != cpol_i)) faults_o[6] = 1;
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if (!have_edge && cycle - segment_start < integer'(setup_i)) faults_o[1] = 1;
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if (frame_edges == 0 && !cpha_i && mosi_i != previous_mosi) faults_o[2] = 1;
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last_edge = cycle;
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have_edge = 1;
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frame_edges = (frame_edges + 1) % (2 * width_bits);
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edges_o++;
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if (!aborted && ((sck_i == cpol_i) == cpha_i)) begin
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index_bit = lsb_i ? samples : width_bits - 1 - samples;
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received[index_bit] = mosi_i;
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samples++;
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if (samples == width_bits) begin
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expected_word = 32'h80ff017e ^ (32'(frames_o / (32 / width_bits)) * 32'h01020408);
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expected_frame = 16'(expected_word >> ((frames_o % (32 / width_bits)) * width_bits));
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if (direction_i == 2) expected_frame = dummy_i;
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if ((received & (frame16_i ? 16'hffff : 16'h00ff)) !==
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(expected_frame & (frame16_i ? 16'hffff : 16'h00ff)))
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faults_o[8] = 1;
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frames_o++;
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samples = 0;
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received = 0;
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end
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end else if (!aborted) begin
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response = reply(frames_o);
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miso_o = response[lsb_i?samples : width_bits-1-samples];
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end
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end else if (!cs_n_i && have_edge && frame_edges != 0 &&
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(!aborted || sck_i != cpol_i) && cycle - last_edge > integer'(divider_i))
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faults_o[0] = 1;
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previous_sck = sck_i;
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previous_cs = cs_n_i;
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previous_mosi = mosi_i;
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end
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end
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endmodule
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