mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
b5cbc89928
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads. - Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves. - Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements. - Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts. - Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
89 lines
5.0 KiB
Tcl
89 lines
5.0 KiB
Tcl
# Source-bound Tiny R2 feasibility only. No timing exceptions are added here.
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source [file join [file dirname [info script]] opensta.tcl]
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set output $::env(TINY_R2_OUTPUT)
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set candidate $::env(TINY_R2_CANDIDATE)
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report_clock_properties > $output/clocks.rpt
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report_checks -path_group clk_system -path_delay max -group_path_count 1 -fields {capacitance slew fanout} > $output/sys-setup.rpt
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report_checks -path_group clk_system -path_delay min -group_path_count 1 -fields {capacitance slew fanout} > $output/sys-hold.rpt
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report_check_types -recovery -removal -min_pulse_width -min_period -max_slew -max_capacitance -max_fanout -violators -verbose > $output/constraint-violations.rpt
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check_setup -verbose > $output/coverage.rpt
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set counts [open $output/reset-loads.tsv w]
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puts $counts "name\tdrivers\tdirect_loads\tstructural_endpoints"
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proc reset_report {label nets {drivers {}}} {
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global output counts
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if {[llength $nets] != 1} { error "expected one reset net for $label" }
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set net [lindex $nets 0]
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if {[llength $drivers] == 0} {
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set drivers [get_pins -of_objects $net -filter {direction == output}]
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}
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if {[llength $drivers] != 1} { error "expected one reset driver for $label" }
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set direct {}
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foreach pin [get_fanout -from $drivers -flat -pin_levels 1 -trace_arcs all] {
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if {[get_property $pin direction] eq "input"} { lappend direct $pin }
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}
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set endpoints [get_fanout -from $drivers -flat -endpoints_only -trace_arcs all]
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puts $counts "$label\t[get_full_name [lindex $drivers 0]]\t[llength $direct]\t[llength $endpoints]"
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report_net [get_full_name $net] > $output/$label-net.rpt
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report_checks -through $drivers -path_delay min_max -group_path_count 10 -fields {capacitance slew fanout} > $output/$label-paths.rpt
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set file [open $output/$label-endpoints.rpt w]
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foreach pin $endpoints { puts $file [get_full_name $pin] }
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close $file
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}
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reset_report system [get_nets -quiet {u_soc.s_rst_n}]
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set leaf_instances [get_cells -hierarchical -quiet {*u_leaf_rst_sync}]
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if {$candidate} {
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if {[llength $leaf_instances] != 17} { error "reset leaves merged or missing" }
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set output_register_pins [get_pins -hierarchical -quiet {*rst_n_o_reg/Q}]
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for {set index 0} {$index < 17} {incr index} {
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set selected {}
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foreach instance $leaf_instances {
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set name [get_full_name $instance]
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if {[regexp {gen_leaf\[([0-9]+)\][.]u_leaf_rst_sync$} $name -> leaf_index] && $leaf_index == $index} {
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lappend selected $instance
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}
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}
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if {[llength $selected] != 1} { error "leaf index missing or duplicated: $index" }
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set name [get_full_name [lindex $selected 0]]
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set driver {}
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foreach pin $output_register_pins {
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if {[get_full_name $pin] eq "$name/rst_n_o_reg/Q"} { lappend driver $pin }
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}
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if {[llength $driver] != 1} { error "mapped leaf output register missing: $name" }
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# Yosys may rename an alias to its APB interface. Resolve the consumed
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# net through the preserved leaf instance, not a source-level wire name.
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set outputs [get_pins -of_objects $selected -filter {direction == output}]
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reset_report leaf-$index [get_nets -of_objects $outputs] $driver
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}
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} elseif {[llength $leaf_instances] != 0} {
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error "pre-change netlist already contains reset leaves"
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}
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close $counts
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set clock_source [get_pins -quiet {u_clock_buffer/clk_o}]
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if {[llength $clock_source] != 1} { error "system clock source missing" }
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set macro_clocks {}
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foreach pin [get_fanout -from $clock_source -flat -pin_levels 1 -trace_arcs all] {
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if {[string match {*/A_CLK} [get_full_name $pin]]} { lappend macro_clocks $pin }
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}
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if {[llength $macro_clocks] != 32} { error "expected 32 direct SYS main-SRAM clock loads" }
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set macros [get_cells -hierarchical -filter {ref_name == RM_IHPSG13_1P_1024x32_c2_bm_bist}]
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if {[llength $macros] != 32} { error "main-SRAM macro binding differs from 32" }
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set file [open $output/sram-clock-pins.rpt w]
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foreach pin $macro_clocks { puts $file [get_full_name $pin] }
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close $file
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set macro_inputs {}
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set macro_outputs {}
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foreach pin [get_pins -of_objects $macros] {
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set name [get_full_name $pin]
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if {[string match {*/A_DOUT*} $name]} { lappend macro_outputs $pin }
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if {[regexp {/A_(ADDR|DIN|BM|WEN|REN|MEN)} $name]} { lappend macro_inputs $pin }
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}
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if {[llength $macro_inputs] == 0 || [llength $macro_outputs] == 0} { error "SRAM data timing pins missing" }
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report_checks -to $macro_inputs -path_delay min_max -group_path_count 20 -fields {capacitance slew fanout} > $output/sram-input-paths.rpt
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report_checks -from $macro_outputs -path_delay min_max -group_path_count 20 -fields {capacitance slew fanout} > $output/sram-return-paths.rpt
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set cpu_pins [get_pins -hierarchical -quiet {*u_cpu*/Q}]
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if {[llength $cpu_pins] == 0} { error "CPU sequential launch pins missing" }
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report_checks -from $cpu_pins -path_delay min_max -group_path_count 20 -fields {capacitance slew fanout} > $output/cpu-paths.rpt
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puts "TINY_R2_FEASIBILITY_PASS: source-bound reports; 32 SYS macros; [llength $leaf_instances] reset leaves"
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