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https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
b5cbc89928
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads. - Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves. - Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements. - Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts. - Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
8 lines
164 B
Plaintext
8 lines
164 B
Plaintext
/top/tiny_axi4_fabric.sv
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/top/tiny_axi42apb4.sv
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/top/tiny_sysctrl.sv
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/top/tiny_archinfo.sv
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/top/tiny_reset_tree.sv
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/top/retrosoc_tiny.sv
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/top/retrosoc_tiny_asic.sv
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