mirror of
https://github.com/retroSoC/retroSoC.git
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maksyuki
2b6819449c
- Added interface to and implemented error handling for register writes. - Introduced a new test for AXI4 address gate functionality in . - Updated clock and reset domain assertions in to reflect new domain names. - Modified expected outputs in to include new clock domains. - Adjusted chip configuration assertions in to account for additional power pads. - Enhanced memory map tests in with new definitions and includes. - Updated pin mapping tests in to include new reference clock pads. - Improved script tools tests in to ensure correct validation of extension bindings. - Refined system control tests in to include new clock control interface. - Updated USB2 packet RAM tests in to include new SRAM definitions. - Enhanced user extensions tests in to validate new product extension configurations. - Adjusted user IP register parity tests to use legacy extensions. - Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
53 lines
2.4 KiB
Markdown
53 lines
2.4 KiB
Markdown
# Hazard3 Management-Core Debug
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## Scope
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The fixed Hazard3 management core always exposes a standard RISC-V JTAG Debug
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Transport Module (DTM) on five ASIC pads: TCK, TMS, TDI, TRST_n, and TDO. The
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default JTAG ID code is `0xDEADBEEF`. Set
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`JTAG_IDCODE=<eight hexadecimal digits>` to use a board-specific value.
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The Debug Module (DM) controls only the management Hazard3 hart. It supports
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abstract register and memory commands and has `HAVE_SBA=0`, so it never becomes
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a second SoC bus master. Debugger memory operations execute through the halted
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hart and remain subject to the AXI4 interconnect access policy. MPW user cores,
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peripherals, clocks, and pad control stay outside the debug-reset scope.
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The product Vexii HP hart can own shared JTAG only while held in reset. C0-C3
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are software-selected only in the mini-ver-mpw compatibility profile; they are
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not management-core options and do not have a management Debug Module.
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## Reset And Clocking
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The DTM runs in the JTAG TCK domain. Hazard3's APB async bridge transfers DMI
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transactions into the LP DM domain. The canonical clock/reset map constrains
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TCK at 10 MHz and declares JTAG asynchronous to LP.
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The DM `ndmreset` and hart-reset requests pass through `mgmt_debug_reset`.
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It waits until the management AHB-Lite-to-AXI4 bridge is idle, then resets only
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that bridge and the management hart. The DTM, DM, RCU, MPW user cores, and all
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peripherals remain live. Reset release is synchronized with the common
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`rst_sync` cell and acknowledged only after the local reset is released.
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## Verilator Acceptance
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The `ihp130-debug` profile builds a minimal SRAM-resident firmware image and
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starts a loopback remote-bitbang endpoint inside the Verilator harness. The
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locked OpenOCD and RISC-V GDB binaries then verify JTAG identification, hart
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register access, SRAM read/write, ELF download, a software breakpoint, resume,
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and single-step.
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```sh
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make CONFIG=configs/ci/ihp130-debug.mk SIMU=VERILATOR debug-sim
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```
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The flow writes `result-debug-sim.json` and the emulator, OpenOCD, and GDB logs
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under `build/<variant>/sim/verilator/debug/`. It passes only when GDB prints
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`DEBUG_GDB_PASS`. This is a functional simulation check, not board-level JTAG
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signal-integrity, DFT, or production debug-lock signoff.
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The OpenOCD configuration is
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`rtl/mini/dv/verilator/openocd/retrosoc_hazard3.cfg`; its remote-bitbang port
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is supplied by the test driver, so concurrent local runs do not share a fixed
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TCP port.
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