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https://github.com/retroSoC/retroSoC.git
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21 lines
1.4 KiB
Tcl
21 lines
1.4 KiB
Tcl
#120MHz
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set clk_period 8.33
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create_clock -period $clk_period [get_ports xi_i_pad]
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create_clock -period $clk_period [get_ports extclk_i_pad]
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create_generated_clock -name CLK_sys_peri -divide_by 1 -source u_xtal_io_pad/clk [get_pins u_sys_mux/clk_o]
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create_generated_clock -name CLK_flash_clk_o -divide_by 1 -source u_retrosoc/u_spimemio/xfer/flash_clk_reg/Q [get_ports flash_clk_o_pad]
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create_generated_clock -name CLK_cust_qspi_spi_clk_o -divide_by 1 -source u_retrosoc/u_axil_ip_wrapper/u_apb_spi_master/u_spictrl/u_clkgen/spi_clk_reg/Q [get_ports cust_qspi_spi_clk_o_pad]
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create_generated_clock -name CLK_cust_psram_sclk_o -divide_by 2 -source u_retrosoc/u_psram/sclk_reg/Q [get_ports cust_psram_sclk_o_pad]
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create_generated_clock -name CLK_cust_spfs_clk_o -divide_by 1 -source u_retrosoc/u_axil_ip_wrapper/u_spi_flash/u0_spi_top/clgen/clk_out_reg/Q [get_ports cust_spfs_clk_o_pad]
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set_false_path -from [get_cells u_rst_sync/RST_SYNC_BLOCK[4].genblk1.u_sync_dffr/dat_o_reg]
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set clk_period_factor .2
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set clk_delay [expr $clk_period * $clk_period_factor]
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# set_input_delay $clk_delay -clock clk {req_val reset resp_rdy req_msg[*]}
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# set_input_delay $clk_delay -clock xi_i_pad {}
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set_output_delay $clk_delay -clock xi_i_pad [all_outputs]
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set_input_transition .1 [all_inputs]
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