mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
bc48cec74a
Integrate the Tiny RCU, normalized REF24 control, external-input profiles, single PLL backend, SYS/MEM/PCLK clocks, CPU-only WFI gating, peripheral lifecycle control and retained debug behavior. Keep CPU and all 32 main SRAM macros on SYS and the six private Crypto macros on PCLK. Add the handwritten RCU register/HAL contract, RS_EBUSY, bounded SDK operations and focused firmware. Preserve shared-IP defaults and the ICS55/PLL SAFE24 boot and explicit IHP130/no-PLL compatibility profiles. Use APB/AXI domain bridges and source-owned response holders to preserve backpressured responses, complete aborted bursts and prevent stale replay. Verify production DMA source-reset drain and common XPI endpoint reset with extracted integration bindings and an independent scoreboard. Add source-bound macro/clock audits, SAFE24 observational STA constraints and commercial-adapter host checks. No P8 functionality or operating-point qualification is included. See TINY-R2-P7 in docs/ip/tiny-soc.md. Validation: 54 P7 directed tests pass, including both simulators, ten source-reset ratio runs and two expected-negative drain mutations. RTL format/style, clock/reset inventory, Ruff and both Tiny PDK PR dry-runs pass. Retained 06-00 synthesis and strict netlist boots pass for both PDKs; STA remains negative and observational. Source comparison confirms only the follow-up tests changed after that backend campaign. Evidence: build/ics55-tiny-2026-10-14-06-00-ff4b5cef6eb5/meta/ tiny-r2-p7-source-reset/summary.json. Earlier firmware, HAL and compatibility results and the non-clean full-suite attempt retain their original attribution. Full Icarus firmware is deferred to final Tiny qualification; this commit does not constitute human phase acceptance or physical signoff.
433 lines
13 KiB
Systemverilog
433 lines
13 KiB
Systemverilog
`timescale 1ns / 1ps
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module tiny_axi4_async_bridge_tb;
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logic src_clk = 1'b0;
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logic dst_clk = 1'b0;
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logic src_rst_n = 1'b0;
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logic dst_rst_n = 1'b0;
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logic clear = 1'b0;
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logic clear_busy;
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logic ready;
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integer sink_ar_count = 0;
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integer sink_aw_count = 0;
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integer source_r_count = 0;
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integer source_b_count = 0;
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logic test_reset_response;
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logic test_write_response;
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always @(posedge src_clk) begin
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if (src_rst_n && source.rvalid && source.rready) source_r_count++;
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if (src_rst_n && source.bvalid && source.bready) source_b_count++;
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end
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always #5 src_clk = !src_clk;
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always #7 dst_clk = !dst_clk;
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) source (
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.aclk (src_clk),
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.aresetn(src_rst_n)
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);
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) sink (
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.aclk (dst_clk),
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.aresetn(dst_rst_n)
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);
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tiny_axi4_async_bridge u_dut (
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.src_clk_i (src_clk),
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.src_rst_n_i (src_rst_n),
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.dst_clk_i (dst_clk),
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.dst_rst_n_i (dst_rst_n),
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.clear_i (clear),
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.clear_busy_o(clear_busy),
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.ready_o (ready),
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.epoch_o (),
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.src_axi4 (source),
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.dst_axi4 (sink)
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);
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always @(posedge dst_clk) begin
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if (dst_rst_n && sink.arvalid && sink.arready) sink_ar_count = sink_ar_count + 1;
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if (dst_rst_n && sink.awvalid && sink.awready) sink_aw_count = sink_aw_count + 1;
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end
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task automatic source_defaults;
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begin
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source.awid = 0;
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source.awaddr = '0;
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source.awlen = 0;
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source.awsize = 2;
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source.awburst = 1;
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source.awlock = 0;
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source.awcache = 0;
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source.awprot = 0;
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source.awqos = 0;
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source.awregion = 0;
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source.awuser = 0;
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source.awvalid = 0;
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source.wdata = 32'h1234_5678;
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source.wstrb = 4'hf;
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source.wlast = 1;
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source.wuser = 0;
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source.wvalid = 0;
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source.bready = 1;
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source.arid = 0;
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source.araddr = '0;
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source.arlen = 0;
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source.arsize = 2;
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source.arburst = 1;
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source.arlock = 0;
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source.arcache = 0;
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source.arprot = 0;
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source.arqos = 0;
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source.arregion = 0;
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source.aruser = 0;
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source.arvalid = 0;
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source.rready = 1;
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end
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endtask
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task automatic sink_defaults;
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begin
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sink.awready = 1;
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sink.wready = 1;
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sink.bid = 0;
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sink.bresp = 0;
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sink.buser = 0;
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sink.bvalid = 0;
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sink.arready = 1;
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sink.rid = 0;
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sink.rdata = 32'hcafe_babe;
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sink.rresp = 0;
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sink.rlast = 1;
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sink.ruser = 0;
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sink.rvalid = 0;
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end
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endtask
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task automatic wait_ready;
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begin
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wait (ready === 1'b1);
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repeat (3) @(posedge src_clk);
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end
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endtask
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task automatic issue_read(input logic [31:0] address);
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begin
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@(negedge src_clk);
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source.araddr = address;
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source.arvalid = 1;
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do @(posedge src_clk); while (!source.arready);
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@(negedge src_clk);
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source.arvalid = 0;
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end
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endtask
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task automatic issue_write(input logic [31:0] address);
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begin
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@(negedge src_clk);
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source.awaddr = address;
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source.awvalid = 1;
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do @(posedge src_clk); while (!source.awready);
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@(negedge src_clk);
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source.awvalid = 0;
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source.wvalid = 1;
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do @(posedge src_clk); while (!source.wready);
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@(negedge src_clk);
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source.wvalid = 0;
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end
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endtask
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initial begin
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source_defaults();
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sink_defaults();
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test_reset_response = $test$plusargs("same_cycle_reset_read") ||
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$test$plusargs("same_cycle_reset_write");
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test_write_response = $test$plusargs("same_cycle_write") ||
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$test$plusargs("held_write_stability") || $test$plusargs("same_cycle_reset_write");
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repeat (5) @(posedge src_clk);
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src_rst_n = 1;
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dst_rst_n = 1;
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wait_ready();
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if ($test$plusargs("clear_pending")) begin
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source.rready = 0;
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issue_read(32'h5400_0010);
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repeat (12) @(negedge dst_clk);
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@(negedge src_clk);
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clear = 1;
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wait (source.rvalid === 1'b1);
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@(negedge src_clk);
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if (source.rresp !== 2'b11) $fatal(1, "SIM_TEST_FAIL clear must return error");
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clear = 0;
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source.rready = 1;
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@(posedge src_clk);
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@(negedge src_clk);
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repeat (200) @(negedge src_clk);
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if (source_r_count != 1 || ready || source.arready)
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$fatal(1, "SIM_TEST_FAIL pending clear lost isolation");
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// A delayed pre-clear response must never complete a new request.
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@(negedge dst_clk);
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sink.rvalid = 1;
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do @(posedge dst_clk); while (!sink.rready);
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@(negedge dst_clk);
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sink.rvalid = 0;
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repeat (20) @(negedge src_clk);
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if (source.rvalid || source_r_count != 1)
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$fatal(1, "SIM_TEST_FAIL late response escaped clear isolation");
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dst_rst_n = 0;
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repeat (8) @(negedge src_clk);
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dst_rst_n = 1;
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wait_ready();
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repeat (20) @(negedge src_clk);
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if (source.rvalid || source_r_count != 1)
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$fatal(1, "SIM_TEST_FAIL late response replay after reset");
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$display("SIM_TEST_PASS Tiny AXI pending-clear quarantine/recovery");
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$finish;
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end
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if ($test$plusargs("burst_abort")) begin
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source.arlen = 3;
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source.arid = 1;
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source.rready = 0;
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issue_read(32'h5400_0100);
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wait (sink.arvalid === 1'b1);
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@(negedge dst_clk);
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sink.rvalid = 1;
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sink.rlast = 0;
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sink.rid = 1;
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do @(posedge dst_clk); while (!sink.rready);
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@(negedge dst_clk);
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sink.rvalid = 0;
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wait (source.rvalid === 1'b1);
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@(negedge src_clk);
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dst_rst_n = 0;
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repeat (8) @(negedge src_clk);
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// Preserve the already exposed first beat; synthesize exactly the three
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// missing error beats, with RLAST only on the original fourth beat.
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for (integer beat = 0; beat < 4; beat++) begin
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wait (source.rvalid === 1'b1);
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@(negedge src_clk);
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if (source.rid !== 1'b1 || source.rlast !== (beat == 3) ||
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source.rresp !== (beat == 0 ? 2'b00 : 2'b11))
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$fatal(1, "SIM_TEST_FAIL reset read burst beat=%0d", beat);
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source.rready = 1;
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@(posedge src_clk);
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@(negedge src_clk);
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source.rready = 0;
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end
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dst_rst_n = 1;
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wait_ready();
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if (source_r_count != 4 || source.rvalid) $fatal(1, "SIM_TEST_FAIL read burst count");
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source.awlen = 3;
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source.awid = 1;
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source.bready = 0;
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@(negedge src_clk);
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source.awvalid = 1;
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do @(posedge src_clk); while (!source.awready);
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@(negedge src_clk);
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source.awvalid = 0;
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dst_rst_n = 0;
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repeat (8) @(negedge src_clk);
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for (integer beat = 0; beat < 4; beat++) begin
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if (source.bvalid) $fatal(1, "SIM_TEST_FAIL reset B before write data drain");
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source.wvalid = 1;
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source.wlast = beat == 3;
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do @(posedge src_clk); while (!source.wready);
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@(negedge src_clk);
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source.wvalid = 0;
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end
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wait (source.bvalid === 1'b1);
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@(negedge src_clk);
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if (source.bid !== 1'b1 || source.bresp !== 2'b11)
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$fatal(1, "SIM_TEST_FAIL reset burst write response");
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source.bready = 1;
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@(posedge src_clk);
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@(negedge src_clk);
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dst_rst_n = 1;
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wait_ready();
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repeat (20) @(negedge src_clk);
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if (source_b_count != 1 || source.bvalid) $fatal(1, "SIM_TEST_FAIL write burst count");
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$display("SIM_TEST_PASS Tiny AXI burst abort conservation");
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$finish;
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end
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if (test_reset_response || $test$plusargs(
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"same_cycle_clear"
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) || $test$plusargs(
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"same_cycle_write"
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) || $test$plusargs(
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"held_read_stability"
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) || $test$plusargs(
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"held_write_stability"
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)) begin
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if (test_write_response) begin
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source.bready = 0;
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issue_write(32'h5400_0020);
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repeat (12) @(negedge dst_clk);
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sink.bvalid = 1;
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do @(posedge dst_clk); while (!sink.bready);
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@(negedge dst_clk);
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sink.bvalid = 0;
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wait (source.bvalid === 1'b1);
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end else begin
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source.rready = 0;
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issue_read(32'h5400_0020);
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wait (sink.arvalid === 1'b1);
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@(negedge dst_clk);
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sink.rvalid = 1;
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do @(posedge dst_clk); while (!sink.rready);
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@(negedge dst_clk);
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sink.rvalid = 0;
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wait (source.rvalid === 1'b1);
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end
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@(negedge src_clk);
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if ($test$plusargs("held_read_stability") || $test$plusargs("held_write_stability")) begin
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// Source reset remains high. A stalled response is still owned by
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// the source interface even when the remote endpoint resets.
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dst_rst_n = 0;
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repeat (8) begin
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@(negedge src_clk);
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if ($test$plusargs(
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"held_read_stability"
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) && (source.rvalid !== 1'b1 || source.rresp !== 2'b00 ||
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source.rdata !== 32'hcafe_babe || source.rlast !== 1'b1))
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$fatal(1, "SIM_TEST_FAIL stalled source R response changed on remote reset");
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if ($test$plusargs(
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"held_write_stability"
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) && (source.bvalid !== 1'b1 || source.bresp !== 2'b00))
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$fatal(1, "SIM_TEST_FAIL stalled source B response changed on remote reset");
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end
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$display("SIM_TEST_PASS Tiny AXI held response stability");
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$finish;
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end
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if (test_reset_response) begin
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dst_rst_n = 0;
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end else begin
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clear = 1;
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wait (u_dut.s_clear_src_pulse === 1'b1);
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@(negedge src_clk);
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end
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source.rready = 1;
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source.bready = 1;
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@(posedge src_clk);
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@(negedge src_clk);
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clear = 0;
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repeat (200) @(negedge src_clk);
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if (test_write_response && source_b_count != 1)
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$fatal(1, "SIM_TEST_FAIL one AW produced %0d B handshakes during clear", source_b_count);
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if (!test_write_response && source_r_count != 1)
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$fatal(1, "SIM_TEST_FAIL one AR produced %0d R handshakes during clear", source_r_count);
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$display("SIM_TEST_PASS Tiny AXI same-cycle clear conservation");
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$finish;
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end
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issue_read(32'h5400_0040);
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wait (sink.arvalid === 1'b1);
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@(negedge dst_clk);
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sink.rvalid = 1;
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do @(posedge dst_clk); while (!sink.rready);
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@(negedge dst_clk);
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sink.rvalid = 0;
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wait (source.rvalid === 1'b1);
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if (source.rresp != 2'b00 || source.rdata != 32'hcafe_babe || !source.rlast)
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$fatal(1, "normal Tiny AXI read response mismatch");
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@(posedge src_clk);
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@(negedge src_clk);
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source.rready = 0;
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issue_read(32'h5400_0060);
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wait (sink.arvalid === 1'b1);
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@(negedge dst_clk);
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sink.rvalid = 1;
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do @(posedge dst_clk); while (!sink.rready);
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@(negedge dst_clk);
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sink.rvalid = 0;
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wait (source.rvalid === 1'b1);
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dst_rst_n = 0;
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wait (u_dut.s_abort_read_q === 1'b1);
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#1;
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if (!source.rvalid || source.rresp != 2'b00 || !source.rlast || source.rdata != 32'hcafe_babe)
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$fatal(1, "remote reset changed held read response");
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source.rready = 1;
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do @(posedge src_clk); while (u_dut.s_abort_read_q);
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source.rready = 0;
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@(negedge dst_clk);
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dst_rst_n = 1;
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wait_ready();
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source.rready = 1;
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issue_read(32'h5400_0080);
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wait (sink.arvalid === 1'b1);
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sink.arready = 0;
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@(negedge dst_clk);
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dst_rst_n = 0;
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wait (source.rvalid === 1'b1);
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if (source.rresp != 2'b11 || !source.rlast || source.rdata != 0)
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$fatal(1, "destination reset did not return read DECERR");
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if (sink.arvalid || sink.awvalid) $fatal(1, "destination reset retained stale request");
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@(negedge dst_clk);
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dst_rst_n = 1;
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sink.arready = 1;
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wait_ready();
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if (sink_ar_count != 2) $fatal(1, "reset replayed the read request");
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sink.awready = 0;
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sink.wready = 0;
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issue_write(32'h5400_00c0);
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wait (sink.awvalid === 1'b1);
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@(negedge dst_clk);
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dst_rst_n = 0;
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wait (source.bvalid === 1'b1);
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if (source.bresp != 2'b11) $fatal(1, "destination reset did not return write DECERR");
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if (sink.arvalid || sink.awvalid || sink.wvalid)
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$fatal(1, "destination reset retained stale write request");
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@(negedge dst_clk);
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dst_rst_n = 1;
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sink.awready = 1;
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sink.wready = 1;
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wait_ready();
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if (sink_aw_count != 0) $fatal(1, "reset replayed the write request");
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source.bready = 0;
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issue_write(32'h5400_00e0);
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repeat (12) @(negedge dst_clk);
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@(negedge dst_clk);
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sink.bvalid = 1;
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do @(posedge dst_clk); while (!sink.bready);
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@(negedge dst_clk);
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sink.bvalid = 0;
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wait (source.bvalid === 1'b1);
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dst_rst_n = 0;
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wait (u_dut.s_abort_write_q === 1'b1);
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#1;
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if (!source.bvalid || source.bresp != 2'b00)
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$fatal(1, "remote reset changed held write response");
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source.bready = 1;
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do @(posedge src_clk); while (u_dut.s_abort_write_q);
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source.bready = 0;
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@(negedge dst_clk);
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dst_rst_n = 1;
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wait_ready();
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source.bready = 1;
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$display("SIM_TEST_PASS Tiny AXI CDC reset abort/error/no-replay");
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$finish;
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end
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initial begin
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#100000;
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$fatal(1, "SIM_TEST_TIMEOUT Tiny AXI CDC");
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end
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endmodule
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