mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
bc48cec74a
Integrate the Tiny RCU, normalized REF24 control, external-input profiles, single PLL backend, SYS/MEM/PCLK clocks, CPU-only WFI gating, peripheral lifecycle control and retained debug behavior. Keep CPU and all 32 main SRAM macros on SYS and the six private Crypto macros on PCLK. Add the handwritten RCU register/HAL contract, RS_EBUSY, bounded SDK operations and focused firmware. Preserve shared-IP defaults and the ICS55/PLL SAFE24 boot and explicit IHP130/no-PLL compatibility profiles. Use APB/AXI domain bridges and source-owned response holders to preserve backpressured responses, complete aborted bursts and prevent stale replay. Verify production DMA source-reset drain and common XPI endpoint reset with extracted integration bindings and an independent scoreboard. Add source-bound macro/clock audits, SAFE24 observational STA constraints and commercial-adapter host checks. No P8 functionality or operating-point qualification is included. See TINY-R2-P7 in docs/ip/tiny-soc.md. Validation: 54 P7 directed tests pass, including both simulators, ten source-reset ratio runs and two expected-negative drain mutations. RTL format/style, clock/reset inventory, Ruff and both Tiny PDK PR dry-runs pass. Retained 06-00 synthesis and strict netlist boots pass for both PDKs; STA remains negative and observational. Source comparison confirms only the follow-up tests changed after that backend campaign. Evidence: build/ics55-tiny-2026-10-14-06-00-ff4b5cef6eb5/meta/ tiny-r2-p7-source-reset/summary.json. Earlier firmware, HAL and compatibility results and the non-clean full-suite attempt retain their original attribution. Full Icarus firmware is deferred to final Tiny qualification; this commit does not constitute human phase acceptance or physical signoff.
88 lines
2.5 KiB
Systemverilog
88 lines
2.5 KiB
Systemverilog
`timescale 1ns / 1ps
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module tiny_clock_reset_subsystem_tb;
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logic ref_clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic [1:0] profile = 2'd0;
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logic apply = 1'b0;
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logic [1:0] current_profile;
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logic busy, fault;
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logic sys_clk, mem_clk, pclk;
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logic sys_rst_n, mem_rst_n, pclk_rst_n;
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logic [31:0] xin_hz, ref_hz, sys_hz, mem_hz, pclk_hz;
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always #5 ref_clk_i = !ref_clk_i;
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tiny_clock_reset_subsystem #(
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.RefClkHz(24_000_000),
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.HavePll (1'b0)
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) u_dut (
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.ref_clk_i (ref_clk_i),
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.rst_n_i (rst_n_i),
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.profile_i (profile),
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.apply_i (apply),
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.idle_i (1'b1),
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.clients_idle_i (1'b1),
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.warm_reset_i (1'b0),
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.timeout_i (32'd512),
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.system_request_i (1'b0),
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.command_ack_i (1'b1),
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.fault_code_o (),
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.done_o (),
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.block_o (),
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.ref_clk_o (),
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.ref_rst_n_o (),
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.system_reset_n_o (),
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.pll_locked_o (),
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.pll_selected_o (),
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.current_profile_o(current_profile),
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.busy_o (busy),
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.fault_o (fault),
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.sys_clk_o (sys_clk),
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.mem_clk_o (mem_clk),
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.pclk_o (pclk),
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.sys_rst_n_o (sys_rst_n),
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.mem_rst_n_o (mem_rst_n),
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.pclk_rst_n_o (pclk_rst_n),
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.xin_hz_o (xin_hz),
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.ref_hz_o (ref_hz),
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.sys_hz_o (sys_hz),
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.mem_hz_o (mem_hz),
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.pclk_hz_o (pclk_hz)
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);
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task automatic apply_profile(input logic [1:0] requested);
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begin
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@(negedge ref_clk_i);
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profile = requested;
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apply = 1'b1;
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@(negedge ref_clk_i);
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apply = 1'b0;
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repeat (600) @(negedge ref_clk_i);
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end
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endtask
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initial begin
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repeat (5) @(negedge ref_clk_i);
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rst_n_i = 1'b1;
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repeat (32) @(negedge ref_clk_i);
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if (current_profile != 0 || sys_hz != 24_000_000 || mem_hz != 24_000_000 ||
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pclk_hz != 24_000_000 || !sys_rst_n || !mem_rst_n || !pclk_rst_n) begin
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$fatal(1, "SAFE24 backend state mismatch");
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end
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apply_profile(2'd1);
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if (current_profile != 1 || fault || sys_hz != 24_000_000) begin
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$fatal(1, "external profile handling mismatch");
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end
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apply_profile(2'd2);
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if (!fault || current_profile != 1) $fatal(1, "unsupported PLL was accepted");
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$display("SIM_TEST_PASS Tiny clock/reset backend");
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$finish;
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end
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initial begin
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#100000;
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$fatal(1, "SIM_TEST_TIMEOUT Tiny clock/reset backend");
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end
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endmodule
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