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maksyuki bd21f792d9 fix: fix pllen output logic
2025-02-14 11:28:59 +08:00
crt
feat: add extern fifo write to the spi wr oper
2025-02-13 10:07:32 +08:00
fpga
feat: add psram ctrl signal
2025-02-13 21:48:29 +08:00
rtl
fix: fix pllen output logic
2025-02-14 11:28:59 +08:00
syn
feat: add PLL lib to the yosys script
2025-02-13 20:33:20 +08:00
tech
fix: fix pll M, N config error
2025-02-13 20:53:37 +08:00
.gitignore
chore: add vcs ignore to the rule file
2025-02-14 10:44:31 +08:00
README.md
Initial commit
2025-01-02 16:25:42 +08:00

README.md

retroSoC

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Description
A Customized ASIC framework for Retro Stuff!
Readme MulanPSL-2.0
13 MiB
0 Stars 1 Watchers 0 Forks
Languages
SystemVerilog 55.2%
Python 25.8%
C 11.4%
Typst 2.7%
Makefile 1.7%
Other 3.1%