mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
85 lines
2.7 KiB
YAML
85 lines
2.7 KiB
YAML
name: test
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on:
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push:
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branches: [ main, dev ]
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pull_request:
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branches: [ main, dev ]
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jobs:
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build:
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runs-on: ubuntu-22.04
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steps:
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- name: Checkout Repository
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uses: actions/checkout@v4
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- name: Download and Extract Verilator Artifact
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run: |
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verilator_path="verilator-artifact"
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mkdir $verilator_path
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wget https://github.com/retroSoC/artifact/releases/download/verilator-v5.046/verilator-v5.046-ubuntu-22.04-gcc.tar.gz
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tar -xvf verilator-v5.046-ubuntu-22.04-gcc.tar.gz -C $verilator_path
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echo "$(pwd)/$verilator_path/bin" >> $GITHUB_PATH
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sudo apt-get update
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sudo apt-get install mold
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- name: Test Verilator Toolchain
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run: |
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verilator --version
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- name: Download and Extract Yosys Artifact
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run: |
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yosys_path="yosys-artifact"
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mkdir $yosys_path
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wget https://github.com/retroSoC/artifact/releases/download/yosys-v0.58/yosys-v0.58-ubuntu-22.04-gcc.tar.gz
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tar -xvf yosys-v0.58-ubuntu-22.04-gcc.tar.gz -C $yosys_path
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echo "$(pwd)/$yosys_path/bin" >> $GITHUB_PATH
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- name: Test Yosys Toolchain
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run: |
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yosys --version
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- name: Download and Extract RISC-V GNU Toolchain Artifact
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run: |
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riscv_toolchain_path="riscv-toolchain-artifact"
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mkdir $riscv_toolchain_path
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wget https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2025.05.01/riscv32-elf-ubuntu-22.04-gcc-nightly-2025.05.01-nightly.tar.xz
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tar -xvf riscv32-elf-ubuntu-22.04-gcc-nightly-2025.05.01-nightly.tar.xz -C $riscv_toolchain_path
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echo "$(pwd)/$riscv_toolchain_path/riscv/bin" >> $GITHUB_PATH
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- name: Test RISCV-V GNU Toolchain
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run: |
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riscv32-unknown-elf-gcc --version
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- name: Setup MPW Repo
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run: |
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pip install tomli
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python3 setup.py
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- name: Download clusterIP
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run: python3 rtl/clusterip/setup.py
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- name: Download 3rd-party IP and models
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run: python3 rtl/ip/setup.py
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- name: Download Open PDK Repo
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run: python3 pdk/setup.py
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- name: Config FatFs and Coremark Repo
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run: python3 app/setup.py
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- name: Compile Firmware
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run: make CORE=MDD IP=MDD SIMU=VERILATOR HAVE_SRAM_IF=NO HAVE_SRAM_MACRO=NO HAVE_PLL=NO ISA=RV32I HAVE_CSR=NO PROG_TYPE=BASE LINK_TYPE=ld2_psram firmware
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- name: Run RTL sim
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run: |
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python3 verilator.py
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make CORE=MDD IP=MDD SIMU=VERILATOR HAVE_SRAM_IF=NO HAVE_SRAM_MACRO=NO HAVE_PLL=NO sim
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- name: Run synth
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run: |
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make CORE=PICORV32 IP=NONE SIMU=VERILATOR SYNTH=YOSYS PDK=IHP130 HAVE_SRAM_IF=NO HAVE_SRAM_MACRO=NO HAVE_PLL=NO RTL_SIM_CORESEL=0 synth
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- name: Success Notification
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run: echo "RTL simulation completed successfully" |