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maksyuki bd82e77432 feat: use extra verilator artifact to replace comp process in aciton file
2026-03-02 15:01:07 +08:00
.github
feat: use extra verilator artifact to replace comp process in aciton file
2026-03-02 15:01:07 +08:00
app
feat: change default bps from 115200 to 921600
2026-01-09 13:17:38 +08:00
crt
feat: update the test of i2s module
2026-01-31 13:31:53 +08:00
fpga/mini
feat: rm tiny design file
2026-02-07 16:25:21 +08:00
pd
feat: add physical deisgn dir
2025-04-19 13:34:25 +08:00
pdk
chore: add BASE type firmware impl
2025-12-21 15:47:05 +08:00
rtl
chore: use default path for yosys plugin loading
2026-03-01 16:06:15 +08:00
sta/mini
feat: add mini gen2 sdc and tcl
2025-12-26 12:44:53 +08:00
syn
chore: use default path for yosys plugin loading
2026-03-01 16:06:15 +08:00
.gitignore
chore: add 3rd party ip setup script
2026-01-24 11:00:42 +08:00
.verible-format
feat: add some community standards documents
2025-09-25 13:46:49 +08:00
CODE_OF_CONDUCT.md
feat: add some community standards documents
2025-09-25 13:46:49 +08:00
CONTRIBUTING.md
feat: add some community standards documents
2025-09-25 13:46:49 +08:00
LICENSE
chore: update license foramt
2025-11-06 10:14:41 +08:00
Makefile
fix: fix the static tRFC value in auto refresh phase
2026-01-24 12:48:48 +08:00
README.md
chore: add BASE type firmware impl
2025-12-21 15:47:05 +08:00
Security.md
chore: add security guide and modify lint rules
2025-11-19 11:59:47 +08:00
setup.py
feat: use extra verilator artifact to replace comp process in aciton file
2026-03-02 15:01:07 +08:00
verilator.py
fix: fix the wrong verilator inc path
2025-12-18 11:26:43 +08:00

README.md

retroSoC

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Description
A Customized ASIC framework for Retro Stuff!
Readme MulanPSL-2.0
13 MiB
0 Stars 1 Watchers 0 Forks
Languages
SystemVerilog 55.6%
Python 25.1%
C 11.4%
Typst 2.8%
Makefile 1.8%
Other 3.2%