mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
c5dfa96c6f
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py. - Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface. - Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors. - Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
137 lines
3.6 KiB
Systemverilog
137 lines
3.6 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module rib_regslice (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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rib_if.slave rib_slv,
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rib_if.master rib_mst
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// verilog_format: on
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);
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localparam FSM_IDLE = 2'd0;
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localparam FSM_REQ = 2'd1;
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localparam FSM_RESP = 2'd2;
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logic [1:0] s_fsm_d, s_fsm_q;
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logic s_rib_mst_valid_d, s_rib_mst_valid_q;
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logic [31:0] s_rib_mst_addr_d, s_rib_mst_addr_q;
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logic [31:0] s_rib_mst_wdata_d, s_rib_mst_wdata_q;
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logic [3:0] s_rib_mst_wstrb_d, s_rib_mst_wstrb_q;
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logic [31:0] s_rib_mst_rdata_d, s_rib_mst_rdata_q;
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logic s_rib_mst_ready_d, s_rib_mst_ready_q;
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// rib mst if
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assign rib_mst.valid = s_rib_mst_valid_q;
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assign rib_mst.addr = s_rib_mst_addr_q;
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assign rib_mst.wdata = s_rib_mst_wdata_q;
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assign rib_mst.wstrb = s_rib_mst_wstrb_q;
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always_comb begin
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s_fsm_d = s_fsm_q;
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s_rib_mst_valid_d = s_rib_mst_valid_q;
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s_rib_mst_addr_d = s_rib_mst_addr_q;
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s_rib_mst_wdata_d = s_rib_mst_wdata_q;
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s_rib_mst_wstrb_d = s_rib_mst_wstrb_q;
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s_rib_mst_ready_d = s_rib_mst_ready_q;
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s_rib_mst_rdata_d = s_rib_mst_rdata_q;
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rib_slv.ready = '0;
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rib_slv.rdata = '0;
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unique case (s_fsm_q)
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FSM_IDLE: begin
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if (rib_slv.valid) begin
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s_fsm_d = FSM_REQ;
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s_rib_mst_valid_d = rib_slv.valid;
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s_rib_mst_addr_d = rib_slv.addr;
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s_rib_mst_wdata_d = rib_slv.wdata;
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s_rib_mst_wstrb_d = rib_slv.wstrb;
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end
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end
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FSM_REQ: begin
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if (rib_mst.ready) begin
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s_fsm_d = FSM_RESP;
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s_rib_mst_valid_d = 1'b0;
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s_rib_mst_ready_d = rib_mst.ready;
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s_rib_mst_rdata_d = rib_mst.rdata;
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end
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end
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FSM_RESP: begin
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s_fsm_d = FSM_IDLE;
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rib_slv.ready = s_rib_mst_ready_q;
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rib_slv.rdata = s_rib_mst_rdata_q;
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end
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default: begin
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s_fsm_d = s_fsm_q;
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s_rib_mst_valid_d = s_rib_mst_valid_q;
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s_rib_mst_addr_d = s_rib_mst_addr_q;
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s_rib_mst_wdata_d = s_rib_mst_wdata_q;
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s_rib_mst_wstrb_d = s_rib_mst_wstrb_q;
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s_rib_mst_ready_d = s_rib_mst_ready_q;
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s_rib_mst_rdata_d = s_rib_mst_rdata_q;
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rib_slv.ready = '0;
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rib_slv.rdata = '0;
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end
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endcase
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end
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dffr #(2) u_fsm_dffr (
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clk_i,
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rst_n_i,
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s_fsm_d,
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s_fsm_q
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);
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dffr #(1) u_rib_mstr_valid_dffr (
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clk_i,
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rst_n_i,
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s_rib_mst_valid_d,
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s_rib_mst_valid_q
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);
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dffr #(32) u_rib_mst_addr_dffr (
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clk_i,
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rst_n_i,
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s_rib_mst_addr_d,
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s_rib_mst_addr_q
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);
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dffr #(32) u_rib_mst_wdata_dffr (
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clk_i,
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rst_n_i,
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s_rib_mst_wdata_d,
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s_rib_mst_wdata_q
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);
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dffr #(4) u_rib_mst_wstrb_dffr (
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clk_i,
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rst_n_i,
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s_rib_mst_wstrb_d,
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s_rib_mst_wstrb_q
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);
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dffr #(32) u_rib_mst_rdata_dffr (
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clk_i,
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rst_n_i,
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s_rib_mst_rdata_d,
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s_rib_mst_rdata_q
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);
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dffr #(1) u_rib_mst_ready_dffr (
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clk_i,
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rst_n_i,
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s_rib_mst_ready_d,
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s_rib_mst_ready_q
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);
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endmodule
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