mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
c5dfa96c6f
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py. - Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface. - Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors. - Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
113 lines
3.3 KiB
Systemverilog
113 lines
3.3 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "mmap_define.svh"
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module soc_topology_rib_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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rib_if rib ();
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`include "soc_rib_interfaces.svh"
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`include "soc_rib_routes.svh"
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always #5 clk_i = ~clk_i;
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task automatic expect_route(input logic [31:0] address, input integer slot,
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input logic [31:0] expected_rdata);
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begin
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@(negedge clk_i);
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rib.addr = address;
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rib.valid = 1'b1;
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#1;
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if (s_slv_sel_d !== (18'd1 << slot)) begin
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$fatal(1, "unexpected target slot for %h", address);
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end
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@(posedge clk_i);
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#1;
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if (!rib.ready || rib.rdata !== expected_rdata) begin
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$fatal(1, "unexpected response for %h", address);
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end
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@(negedge clk_i);
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rib.valid = 1'b0;
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@(posedge clk_i);
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end
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endtask
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task automatic expect_disabled(input logic [31:0] address);
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begin
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@(negedge clk_i);
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rib.addr = address;
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rib.valid = 1'b1;
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#1;
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if (s_slv_sel_d !== '0) begin
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$fatal(1, "disabled target accepted %h", address);
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end
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@(posedge clk_i);
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#1;
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if (rib.ready || rib.rdata !== '0) begin
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$fatal(1, "disabled target responded to %h", address);
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end
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@(negedge clk_i);
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rib.valid = 1'b0;
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@(posedge clk_i);
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end
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endtask
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initial begin
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rib.valid = 1'b0;
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rib.addr = '0;
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rib.wdata = '0;
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rib.wstrb = '0;
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u_uart_rib_if.ready = 1'b1;
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u_gpio_rib_if.ready = 1'b1;
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u_tim0_rib_if.ready = 1'b1;
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u_tim1_rib_if.ready = 1'b1;
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u_psram_rib_if.ready = 1'b1;
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u_spisd_rib_if.ready = 1'b1;
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u_i2c0_rib_if.ready = 1'b1;
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u_i2s_rib_if.ready = 1'b1;
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u_onewire_rib_if.ready = 1'b1;
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u_xpi_rib_if.ready = 1'b1;
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u_dma_rib_if.ready = 1'b1;
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u_sysctrl_rib_if.ready = 1'b1;
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u_clint_rib_if.ready = 1'b1;
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u_sdram_rib_if.ready = 1'b1;
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u_dvp_rib_if.ready = 1'b1;
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u_sdio_rib_if.ready = 1'b1;
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u_opipsram_rib_if.ready = 1'b1;
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u_i2c1_rib_if.ready = 1'b1;
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u_uart_rib_if.rdata = 32'h0000_0000;
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u_gpio_rib_if.rdata = 32'h1111_1111;
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u_tim0_rib_if.rdata = 32'h2222_2222;
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u_tim1_rib_if.rdata = 32'h3333_3333;
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u_psram_rib_if.rdata = 32'h4444_4444;
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u_spisd_rib_if.rdata = 32'h5555_5555;
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u_i2c0_rib_if.rdata = 32'h6666_6666;
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u_i2s_rib_if.rdata = 32'h7777_7777;
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u_onewire_rib_if.rdata = 32'h8888_8888;
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u_xpi_rib_if.rdata = 32'h9999_9999;
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u_dma_rib_if.rdata = 32'hAAAA_AAAA;
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u_sysctrl_rib_if.rdata = 32'hBBBB_BBBB;
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u_clint_rib_if.rdata = 32'hCCCC_CCCC;
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u_sdram_rib_if.rdata = 32'hDDDD_DDDD;
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u_dvp_rib_if.rdata = 32'hEEEE_EEEE;
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u_sdio_rib_if.rdata = 32'hF0F0_F0F0;
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u_opipsram_rib_if.rdata = 32'h0F0F_0F0F;
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u_i2c1_rib_if.rdata = 32'h1234_5678;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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expect_route(`SOC_ADDR_RIB_GPIO_BASE, 1, 32'h1111_1111);
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expect_route(`SOC_ADDR_PSRAM_BASE, 4, 32'h4444_4444);
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expect_route(`SOC_ADDR_FLASH_BASE, 9, 32'h9999_9999);
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expect_route(`SOC_ADDR_RIB_I2C1_BASE, 17, 32'h1234_5678);
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expect_disabled(`SOC_ADDR_RIB_SDIO_BASE);
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$display("SoC topology RIB routing test passed");
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$finish;
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end
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endmodule
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