mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
c5dfa96c6f
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py. - Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface. - Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors. - Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
85 lines
2.3 KiB
Systemverilog
85 lines
2.3 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
|
|
// retroSoC is licensed under Mulan PSL v2.
|
|
// You can use this software according to the terms and conditions of the Mulan PSL v2.
|
|
// You may obtain a copy of Mulan PSL v2 at:
|
|
// http://license.coscl.org.cn/MulanPSL2
|
|
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
|
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
|
// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
|
|
// See the Mulan PSL v2 for more details.
|
|
|
|
`ifndef RIB_SDRAM_DEF_SV
|
|
`define RIB_SDRAM_DEF_SV
|
|
|
|
// verilog_format: off
|
|
`define RIB_SDRAM_CLKDIV 8'h00
|
|
`define RIB_SDRAM_CFG 8'h04
|
|
// verilog_format: on
|
|
|
|
`endif
|
|
|
|
module sdram_reg (
|
|
// verilog_format: off
|
|
input logic clk_i,
|
|
input logic rst_n_i,
|
|
rib_if.slave rib,
|
|
output logic [1:0] clkdiv_o
|
|
// verilog_format: on
|
|
);
|
|
// rib
|
|
logic s_rib_wr_hdshk, s_rib_rd_hdshk;
|
|
logic s_rib_ready_d, s_rib_ready_q;
|
|
logic s_rib_rdata_en;
|
|
logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
|
|
// register
|
|
logic s_sdram_clkdiv_en;
|
|
logic [1:0] s_sdram_clkdiv_d, s_sdram_clkdiv_q;
|
|
|
|
// rib
|
|
assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
|
|
assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
|
|
assign rib.ready = s_rib_ready_q;
|
|
assign rib.rdata = s_rib_rdata_q;
|
|
// reg
|
|
assign clkdiv_o = s_sdram_clkdiv_q;
|
|
|
|
|
|
assign s_sdram_clkdiv_en = s_rib_wr_hdshk && rib.addr[7:0] == `RIB_SDRAM_CLKDIV;
|
|
assign s_sdram_clkdiv_d = rib.wdata[1:0];
|
|
dffer #(2) u_sdram_clkdiv_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_sdram_clkdiv_en,
|
|
s_sdram_clkdiv_d,
|
|
s_sdram_clkdiv_q
|
|
);
|
|
|
|
|
|
// rib resp
|
|
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
|
|
dffr #(1) u_rib_ready_dffr (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_rib_ready_d,
|
|
s_rib_ready_q
|
|
);
|
|
|
|
|
|
assign s_rib_rdata_en = s_rib_rd_hdshk;
|
|
always_comb begin
|
|
s_rib_rdata_d = s_rib_rdata_q;
|
|
unique case (rib.addr[7:0])
|
|
`RIB_SDRAM_CLKDIV: s_rib_rdata_d = {30'd0, s_sdram_clkdiv_q};
|
|
default: s_rib_rdata_d = s_rib_rdata_q;
|
|
endcase
|
|
end
|
|
dffer #(32) u_rib_rdata_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_rib_rdata_en,
|
|
s_rib_rdata_d,
|
|
s_rib_rdata_q
|
|
);
|
|
|
|
endmodule
|