mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
c5dfa96c6f
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py. - Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface. - Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors. - Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
609 lines
22 KiB
Systemverilog
609 lines
22 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "user_extensions.svh"
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`include "mmap_define.svh"
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`include "soc_rib_defs.svh"
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interface sysctrl_if ();
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logic [`USER_CORESEL_WIDTH-1:0] core_sel_o;
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logic [ `USER_CORE_COUNT-1:0] core_reset_o;
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logic user_bus_enable_o;
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logic user_bus_idle_i;
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logic fault_access_i;
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logic [ 1:0] fault_master_i;
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logic [ 2:0] fault_code_i;
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logic perf_enable_o;
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logic perf_clear_o;
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logic [ 63:0] perf_mgmt_wait_i;
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logic [ 63:0] perf_user_wait_i;
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logic [ 63:0] perf_dma_wait_i;
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logic [ 63:0] perf_rib_wait_i;
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logic [ 63:0] perf_apb_wait_i;
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logic [ 63:0] perf_sdram_wait_i;
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logic [ 63:0] perf_psram_wait_i;
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logic [ 63:0] perf_flash_wait_i;
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logic [ `USER_IPSEL_WIDTH-1:0] ip_sel_o;
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modport dut(
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input user_bus_idle_i,
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input fault_access_i,
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input fault_master_i,
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input fault_code_i,
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input perf_mgmt_wait_i,
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input perf_user_wait_i,
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input perf_dma_wait_i,
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input perf_rib_wait_i,
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input perf_apb_wait_i,
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input perf_sdram_wait_i,
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input perf_psram_wait_i,
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input perf_flash_wait_i,
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output core_sel_o,
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output core_reset_o,
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output user_bus_enable_o,
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output ip_sel_o,
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output perf_enable_o,
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output perf_clear_o
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);
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endinterface
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module rib_sysctrl (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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input logic fault_valid_i,
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input logic [31:0] fault_addr_i,
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input logic [3:0] fault_wstrb_i,
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input logic fault_reserved_i,
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rib_if.slave rib,
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sysctrl_if.dut sysctrl,
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pll_ctrl_if.sysctrl pll_ctrl
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// verilog_format: on
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);
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typedef logic [7:0] sysctrl_offset_t;
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localparam sysctrl_offset_t SYSCTRL_CORESEL_OFFSET = sysctrl_offset_t'(`SOC_SYSCTRL_CORESEL_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_IPSEL_OFFSET = sysctrl_offset_t'(`SOC_SYSCTRL_IPSEL_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PLL_CFG_OFFSET = sysctrl_offset_t'(`SOC_SYSCTRL_PLL_CFG_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PLL_CMD_OFFSET = sysctrl_offset_t'(`SOC_SYSCTRL_PLL_CMD_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_FAULT_STATUS_OFFSET = sysctrl_offset_t'(`SOC_SYSCTRL_FAULT_STATUS_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_FAULT_ADDR_OFFSET = sysctrl_offset_t'(`SOC_SYSCTRL_FAULT_ADDR_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_FAULT_COUNT_OFFSET = sysctrl_offset_t'(`SOC_SYSCTRL_FAULT_COUNT_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PLL_STATUS_OFFSET = sysctrl_offset_t'(`SOC_SYSCTRL_PLL_STATUS_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_USER_CORE_RESET_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_USER_CORE_RESET_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_USER_CORE_STATUS_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_USER_CORE_STATUS_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_FAULT_MASTER_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_FAULT_MASTER_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_FAULT_DETAIL_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_FAULT_DETAIL_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_CTRL_OFFSET = sysctrl_offset_t'(`SOC_SYSCTRL_PERF_CTRL_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_USER_WAIT_LO_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_USER_WAIT_LO_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_USER_WAIT_HI_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_USER_WAIT_HI_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_DMA_WAIT_LO_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_DMA_WAIT_HI_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_RIB_WAIT_LO_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_RIB_WAIT_LO_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_RIB_WAIT_HI_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_RIB_WAIT_HI_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_APB_WAIT_LO_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_APB_WAIT_LO_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_APB_WAIT_HI_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_APB_WAIT_HI_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET);
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localparam sysctrl_offset_t SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET =
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sysctrl_offset_t'(`SOC_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET);
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logic s_rib_wr_hdshk, s_rib_rd_hdshk;
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logic s_rib_ready_d, s_rib_ready_q;
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logic s_rib_rdata_en;
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logic [31:0] s_rib_rdata_d, s_rib_rdata_q;
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logic [`USER_CORESEL_WIDTH-1:0] s_sysctrl_coresel_d, s_sysctrl_coresel_q;
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logic s_sysctrl_coresel_en;
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logic s_sysctrl_coresel_write_valid;
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logic [`USER_CORE_COUNT-1:0] s_user_reset_d, s_user_reset_q;
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logic s_user_reset_en;
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logic s_user_running_d, s_user_running_q;
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logic s_user_draining_d, s_user_draining_q;
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logic s_user_config_error_d, s_user_config_error_q;
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logic s_user_config_error_clear;
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logic s_user_reset_write_legal;
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logic [`USER_CORE_COUNT-1:0] s_user_reset_write_data;
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logic s_sysctrl_ipsel_en;
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logic [`USER_IPSEL_WIDTH-1:0] s_sysctrl_ipsel_d, s_sysctrl_ipsel_q;
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logic [2:0] s_pll_cfg_d, s_pll_cfg_q;
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logic s_pll_cfg_en;
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logic s_pll_apply, s_pll_clear_error;
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logic s_pll_req_valid_d, s_pll_req_valid_q;
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logic s_pll_busy_d, s_pll_busy_q;
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logic s_pll_rsp_accept;
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logic s_pll_error_d, s_pll_error_q;
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logic [1:0] s_pll_error_reason_d, s_pll_error_reason_q;
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logic [2:0] s_pll_active_sel_d, s_pll_active_sel_q;
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logic s_pll_active_valid_d, s_pll_active_valid_q;
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logic s_pll_safe_clk_d, s_pll_safe_clk_q;
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logic s_pll_lock_d, s_pll_lock_q;
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logic s_fault_status_clear;
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logic s_fault_pending_d, s_fault_pending_q;
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logic s_fault_write_d, s_fault_write_q;
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logic [2:0] s_fault_reason_d, s_fault_reason_q;
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logic [2:0] s_fault_detail_d, s_fault_detail_q;
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logic [31:0] s_fault_addr_d, s_fault_addr_q;
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logic [31:0] s_fault_count_d, s_fault_count_q;
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logic [1:0] s_fault_master_d, s_fault_master_q;
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logic s_perf_enable_d, s_perf_enable_q;
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logic s_perf_enable_en, s_perf_clear, s_perf_snapshot;
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logic [63:0] s_perf_mgmt_wait_q;
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logic [63:0] s_perf_user_wait_q;
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logic [63:0] s_perf_dma_wait_q;
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logic [63:0] s_perf_rib_wait_q;
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logic [63:0] s_perf_apb_wait_q;
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logic [63:0] s_perf_sdram_wait_q;
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logic [63:0] s_perf_psram_wait_q;
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logic [63:0] s_perf_flash_wait_q;
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assign s_rib_wr_hdshk = rib.valid && (~s_rib_ready_q) && (|rib.wstrb);
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assign s_rib_rd_hdshk = rib.valid && (~s_rib_ready_q) && (~(|rib.wstrb));
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assign rib.ready = s_rib_ready_q;
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assign rib.rdata = s_rib_rdata_q;
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assign sysctrl.ip_sel_o = s_sysctrl_ipsel_q;
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assign sysctrl.core_sel_o = s_sysctrl_coresel_q;
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assign sysctrl.core_reset_o = s_user_reset_q;
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assign sysctrl.user_bus_enable_o = s_user_running_q;
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assign sysctrl.perf_enable_o = s_perf_enable_q;
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assign sysctrl.perf_clear_o = s_perf_clear;
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assign pll_ctrl.req_sel_o = s_pll_cfg_q;
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assign pll_ctrl.req_valid_o = s_pll_req_valid_q;
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assign pll_ctrl.rsp_ready_o = 1'b1;
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assign s_sysctrl_coresel_write_valid = rib.wdata[`USER_CORESEL_WIDTH-1:0] < `USER_CORE_COUNT;
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assign s_sysctrl_coresel_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_CORESEL_OFFSET &&
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rib.wstrb[0] && s_sysctrl_coresel_write_valid &&
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(&s_user_reset_q) && sysctrl.user_bus_idle_i && ~s_user_running_q;
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assign s_sysctrl_coresel_d = rib.wdata[`USER_CORESEL_WIDTH-1:0];
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dffer #(`USER_CORESEL_WIDTH) u_sysctrl_coresel_dffer (
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clk_i,
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rst_n_i,
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s_sysctrl_coresel_en,
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s_sysctrl_coresel_d,
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s_sysctrl_coresel_q
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);
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assign s_user_reset_write_data = rib.wdata[`USER_CORE_COUNT-1:0];
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assign s_user_reset_write_legal = (&s_user_reset_write_data) ||
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((s_sysctrl_coresel_q < `USER_CORE_COUNT) &&
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((~s_user_reset_write_data) ==
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({{(`USER_CORE_COUNT - 1){1'b0}}, 1'b1} << s_sysctrl_coresel_q)));
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assign s_user_reset_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_USER_CORE_RESET_OFFSET &&
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rib.wstrb[0];
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assign s_user_config_error_clear = s_rib_wr_hdshk &&
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rib.addr[7:0] == SYSCTRL_USER_CORE_STATUS_OFFSET && rib.wstrb[1] && rib.wdata[11];
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always_comb begin
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s_user_reset_d = s_user_reset_q;
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s_user_running_d = s_user_running_q;
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s_user_draining_d = s_user_draining_q;
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s_user_config_error_d = s_user_config_error_q;
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if (s_user_config_error_clear) begin
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s_user_config_error_d = 1'b0;
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end
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if (s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_CORESEL_OFFSET && ~s_sysctrl_coresel_en) begin
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s_user_config_error_d = 1'b1;
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end
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if (s_user_reset_en) begin
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if (~s_user_reset_write_legal) begin
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s_user_config_error_d = 1'b1;
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end else if (&s_user_reset_write_data) begin
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s_user_running_d = 1'b0;
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if (sysctrl.user_bus_idle_i) begin
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s_user_reset_d = s_user_reset_write_data;
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s_user_draining_d = 1'b0;
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end else begin
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s_user_draining_d = 1'b1;
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end
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end else if (sysctrl.user_bus_idle_i && (&s_user_reset_q) && ~s_user_running_q) begin
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s_user_reset_d = s_user_reset_write_data;
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s_user_running_d = 1'b1;
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s_user_draining_d = 1'b0;
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end else begin
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s_user_config_error_d = 1'b1;
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end
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end
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if (s_user_draining_q && sysctrl.user_bus_idle_i) begin
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s_user_reset_d = '1;
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s_user_draining_d = 1'b0;
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end
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end
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dffrc #(`USER_CORE_COUNT, '1) u_user_reset_dffrc (
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clk_i,
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rst_n_i,
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s_user_reset_d,
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s_user_reset_q
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);
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dffr #(1) u_user_running_dffr (
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clk_i,
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rst_n_i,
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s_user_running_d,
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s_user_running_q
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);
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dffr #(1) u_user_draining_dffr (
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clk_i,
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rst_n_i,
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s_user_draining_d,
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s_user_draining_q
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);
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dffr #(1) u_user_config_error_dffr (
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clk_i,
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rst_n_i,
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s_user_config_error_d,
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s_user_config_error_q
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);
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assign s_sysctrl_ipsel_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_IPSEL_OFFSET;
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assign s_sysctrl_ipsel_d = rib.wdata[`USER_IPSEL_WIDTH-1:0];
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dffer #(`USER_IPSEL_WIDTH) u_sysctrl_ipsel_dffer (
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clk_i,
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rst_n_i,
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s_sysctrl_ipsel_en,
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s_sysctrl_ipsel_d,
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s_sysctrl_ipsel_q
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);
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assign s_pll_cfg_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_PLL_CFG_OFFSET && rib.wstrb[0];
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assign s_pll_cfg_d = rib.wdata[2:0];
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dffer #(3) u_pll_cfg_dffer (
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clk_i,
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rst_n_i,
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s_pll_cfg_en,
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s_pll_cfg_d,
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s_pll_cfg_q
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);
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assign s_pll_apply = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET &&
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rib.wstrb[0] && rib.wdata[0];
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assign s_pll_clear_error = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_PLL_CMD_OFFSET &&
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rib.wstrb[0] && rib.wdata[1];
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assign s_pll_rsp_accept = pll_ctrl.rsp_valid_i && pll_ctrl.rsp_ready_o;
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always_comb begin
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s_pll_req_valid_d = s_pll_req_valid_q;
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s_pll_busy_d = s_pll_busy_q;
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if (s_pll_req_valid_q && pll_ctrl.req_ready_i) begin
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s_pll_req_valid_d = 1'b0;
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end
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if (s_pll_apply && ~s_pll_busy_q && ~s_pll_req_valid_q) begin
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s_pll_req_valid_d = 1'b1;
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s_pll_busy_d = 1'b1;
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end
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if (s_pll_rsp_accept) begin
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s_pll_busy_d = 1'b0;
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end
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end
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dffr #(1) u_pll_req_valid_dffr (
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clk_i,
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rst_n_i,
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s_pll_req_valid_d,
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s_pll_req_valid_q
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);
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dffr #(1) u_pll_busy_dffr (
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clk_i,
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rst_n_i,
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s_pll_busy_d,
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s_pll_busy_q
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);
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always_comb begin
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s_pll_error_d = s_pll_error_q;
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s_pll_error_reason_d = s_pll_error_reason_q;
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if (s_pll_clear_error) begin
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s_pll_error_d = 1'b0;
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s_pll_error_reason_d = 2'd0;
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end
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if (s_pll_apply && (s_pll_busy_q || s_pll_req_valid_q)) begin
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s_pll_error_d = 1'b1;
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s_pll_error_reason_d = 2'd3;
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end
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if (s_pll_rsp_accept && |pll_ctrl.rsp_error_i) begin
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s_pll_error_d = 1'b1;
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s_pll_error_reason_d = pll_ctrl.rsp_error_i;
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end
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end
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dffr #(1) u_pll_error_dffr (
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clk_i,
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rst_n_i,
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s_pll_error_d,
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s_pll_error_q
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);
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dffr #(2) u_pll_error_reason_dffr (
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clk_i,
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rst_n_i,
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s_pll_error_reason_d,
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s_pll_error_reason_q
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);
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assign s_pll_active_sel_d = pll_ctrl.rsp_active_sel_i;
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dffer #(3) u_pll_active_sel_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_pll_rsp_accept,
|
|
s_pll_active_sel_d,
|
|
s_pll_active_sel_q
|
|
);
|
|
assign s_pll_active_valid_d = pll_ctrl.rsp_active_valid_i;
|
|
dffer #(1) u_pll_active_valid_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_pll_rsp_accept,
|
|
s_pll_active_valid_d,
|
|
s_pll_active_valid_q
|
|
);
|
|
assign s_pll_safe_clk_d = pll_ctrl.rsp_safe_clk_i;
|
|
dfferc #(1, 1'b1) u_pll_safe_clk_dfferc (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_pll_rsp_accept,
|
|
s_pll_safe_clk_d,
|
|
s_pll_safe_clk_q
|
|
);
|
|
assign s_pll_lock_d = pll_ctrl.rsp_pll_lock_i;
|
|
dffer #(1) u_pll_lock_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_pll_rsp_accept,
|
|
s_pll_lock_d,
|
|
s_pll_lock_q
|
|
);
|
|
|
|
assign s_perf_enable_en = s_rib_wr_hdshk && rib.addr[7:0] == SYSCTRL_PERF_CTRL_OFFSET &&
|
|
rib.wstrb[0];
|
|
assign s_perf_enable_d = rib.wdata[0];
|
|
assign s_perf_clear = s_perf_enable_en && rib.wdata[1];
|
|
assign s_perf_snapshot = s_perf_enable_en && rib.wdata[2];
|
|
dffer #(1) u_perf_enable_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_perf_enable_en,
|
|
s_perf_enable_d,
|
|
s_perf_enable_q
|
|
);
|
|
dffer #(64) u_perf_mgmt_wait_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_perf_snapshot,
|
|
sysctrl.perf_mgmt_wait_i,
|
|
s_perf_mgmt_wait_q
|
|
);
|
|
dffer #(64) u_perf_user_wait_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_perf_snapshot,
|
|
sysctrl.perf_user_wait_i,
|
|
s_perf_user_wait_q
|
|
);
|
|
dffer #(64) u_perf_dma_wait_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_perf_snapshot,
|
|
sysctrl.perf_dma_wait_i,
|
|
s_perf_dma_wait_q
|
|
);
|
|
dffer #(64) u_perf_rib_wait_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_perf_snapshot,
|
|
sysctrl.perf_rib_wait_i,
|
|
s_perf_rib_wait_q
|
|
);
|
|
dffer #(64) u_perf_apb_wait_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_perf_snapshot,
|
|
sysctrl.perf_apb_wait_i,
|
|
s_perf_apb_wait_q
|
|
);
|
|
dffer #(64) u_perf_sdram_wait_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_perf_snapshot,
|
|
sysctrl.perf_sdram_wait_i,
|
|
s_perf_sdram_wait_q
|
|
);
|
|
dffer #(64) u_perf_psram_wait_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_perf_snapshot,
|
|
sysctrl.perf_psram_wait_i,
|
|
s_perf_psram_wait_q
|
|
);
|
|
dffer #(64) u_perf_flash_wait_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_perf_snapshot,
|
|
sysctrl.perf_flash_wait_i,
|
|
s_perf_flash_wait_q
|
|
);
|
|
|
|
assign s_fault_status_clear = s_rib_wr_hdshk &&
|
|
rib.addr[7:0] == SYSCTRL_FAULT_STATUS_OFFSET &&
|
|
rib.wstrb[0] && rib.wdata[0];
|
|
always_comb begin
|
|
s_fault_pending_d = s_fault_pending_q;
|
|
s_fault_write_d = s_fault_write_q;
|
|
s_fault_reason_d = s_fault_reason_q;
|
|
s_fault_detail_d = s_fault_detail_q;
|
|
s_fault_addr_d = s_fault_addr_q;
|
|
s_fault_count_d = s_fault_count_q;
|
|
if (s_fault_status_clear) begin
|
|
s_fault_pending_d = 1'b0;
|
|
end
|
|
if (fault_valid_i) begin
|
|
s_fault_pending_d = 1'b1;
|
|
if (~s_fault_pending_q || s_fault_status_clear) begin
|
|
s_fault_write_d = |fault_wstrb_i;
|
|
s_fault_detail_d = |sysctrl.fault_code_i ? sysctrl.fault_code_i :
|
|
sysctrl.fault_access_i ? `SOC_RIB_RESP_PROTERR :
|
|
fault_reserved_i ? `SOC_RIB_RESP_RESERVED : `SOC_RIB_RESP_DECERR;
|
|
unique case (s_fault_detail_d)
|
|
`SOC_RIB_RESP_RESERVED: s_fault_reason_d = 3'd2;
|
|
`SOC_RIB_RESP_PROTERR: s_fault_reason_d = 3'd3;
|
|
`SOC_RIB_RESP_SLVERR: s_fault_reason_d = 3'd4;
|
|
`SOC_RIB_RESP_TIMEOUT: s_fault_reason_d = 3'd5;
|
|
default: s_fault_reason_d = 3'd1;
|
|
endcase
|
|
s_fault_addr_d = fault_addr_i;
|
|
end
|
|
if (~(&s_fault_count_q)) begin
|
|
s_fault_count_d = s_fault_count_q + 32'd1;
|
|
end
|
|
end
|
|
end
|
|
dffr #(1) u_fault_pending_dffr (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_fault_pending_d,
|
|
s_fault_pending_q
|
|
);
|
|
dffr #(1) u_fault_write_dffr (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_fault_write_d,
|
|
s_fault_write_q
|
|
);
|
|
dffr #(3) u_fault_reason_dffr (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_fault_reason_d,
|
|
s_fault_reason_q
|
|
);
|
|
dffr #(3) u_fault_detail_dffr (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_fault_detail_d,
|
|
s_fault_detail_q
|
|
);
|
|
dffr #(32) u_fault_addr_dffr (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_fault_addr_d,
|
|
s_fault_addr_q
|
|
);
|
|
dffr #(32) u_fault_count_dffr (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_fault_count_d,
|
|
s_fault_count_q
|
|
);
|
|
always_comb begin
|
|
s_fault_master_d = s_fault_master_q;
|
|
if (fault_valid_i && (~s_fault_pending_q || s_fault_status_clear)) begin
|
|
s_fault_master_d = sysctrl.fault_master_i;
|
|
end
|
|
end
|
|
dffr #(2) u_fault_master_dffr (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_fault_master_d,
|
|
s_fault_master_q
|
|
);
|
|
|
|
assign s_rib_ready_d = rib.valid && (~s_rib_ready_q);
|
|
dffr #(1) u_rib_ready_dffr (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_rib_ready_d,
|
|
s_rib_ready_q
|
|
);
|
|
|
|
assign s_rib_rdata_en = s_rib_rd_hdshk;
|
|
always_comb begin
|
|
s_rib_rdata_d = s_rib_rdata_q;
|
|
unique case (rib.addr[7:0])
|
|
// verilog_format: off
|
|
SYSCTRL_CORESEL_OFFSET: s_rib_rdata_d = {{(32 - `USER_CORESEL_WIDTH) {1'b0}}, s_sysctrl_coresel_q};
|
|
SYSCTRL_IPSEL_OFFSET: s_rib_rdata_d = {{(32 - `USER_IPSEL_WIDTH) {1'b0}}, s_sysctrl_ipsel_q};
|
|
SYSCTRL_PLL_CFG_OFFSET: s_rib_rdata_d = {29'd0, s_pll_cfg_q};
|
|
SYSCTRL_FAULT_STATUS_OFFSET: s_rib_rdata_d = {27'd0, s_fault_reason_q, s_fault_write_q, s_fault_pending_q};
|
|
SYSCTRL_FAULT_ADDR_OFFSET: s_rib_rdata_d = s_fault_addr_q;
|
|
SYSCTRL_FAULT_COUNT_OFFSET: s_rib_rdata_d = s_fault_count_q;
|
|
SYSCTRL_PLL_STATUS_OFFSET: s_rib_rdata_d = {
|
|
21'd0,
|
|
pll_ctrl.capable_i,
|
|
s_pll_lock_q,
|
|
s_pll_safe_clk_q,
|
|
s_pll_error_reason_q,
|
|
s_pll_error_q,
|
|
s_pll_busy_q,
|
|
s_pll_active_valid_q,
|
|
s_pll_active_sel_q
|
|
};
|
|
SYSCTRL_USER_CORE_RESET_OFFSET: s_rib_rdata_d = {{(32 - `USER_CORE_COUNT) {1'b0}}, s_user_reset_q};
|
|
SYSCTRL_USER_CORE_STATUS_OFFSET: s_rib_rdata_d = {
|
|
20'd0,
|
|
s_user_config_error_q,
|
|
s_user_draining_q,
|
|
sysctrl.user_bus_idle_i,
|
|
s_user_running_q,
|
|
{ (8 - `USER_CORESEL_WIDTH) {1'b0} },
|
|
s_sysctrl_coresel_q
|
|
};
|
|
SYSCTRL_FAULT_MASTER_OFFSET: s_rib_rdata_d = {30'd0, s_fault_master_q};
|
|
SYSCTRL_FAULT_DETAIL_OFFSET: s_rib_rdata_d = {29'd0, s_fault_detail_q};
|
|
SYSCTRL_PERF_CTRL_OFFSET: s_rib_rdata_d = {31'd0, s_perf_enable_q};
|
|
SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_mgmt_wait_q[31:0];
|
|
SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_mgmt_wait_q[63:32];
|
|
SYSCTRL_PERF_USER_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_user_wait_q[31:0];
|
|
SYSCTRL_PERF_USER_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_user_wait_q[63:32];
|
|
SYSCTRL_PERF_DMA_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_dma_wait_q[31:0];
|
|
SYSCTRL_PERF_DMA_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_dma_wait_q[63:32];
|
|
SYSCTRL_PERF_RIB_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_rib_wait_q[31:0];
|
|
SYSCTRL_PERF_RIB_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_rib_wait_q[63:32];
|
|
SYSCTRL_PERF_APB_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_apb_wait_q[31:0];
|
|
SYSCTRL_PERF_APB_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_apb_wait_q[63:32];
|
|
SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_sdram_wait_q[31:0];
|
|
SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_sdram_wait_q[63:32];
|
|
SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_psram_wait_q[31:0];
|
|
SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_psram_wait_q[63:32];
|
|
SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET: s_rib_rdata_d = s_perf_flash_wait_q[31:0];
|
|
SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET: s_rib_rdata_d = s_perf_flash_wait_q[63:32];
|
|
default: s_rib_rdata_d = s_rib_rdata_q;
|
|
endcase
|
|
// verilog_format: on
|
|
end
|
|
dffer #(32) u_rib_rdata_dffer (
|
|
clk_i,
|
|
rst_n_i,
|
|
s_rib_rdata_en,
|
|
s_rib_rdata_d,
|
|
s_rib_rdata_q
|
|
);
|
|
|
|
endmodule
|