mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
c5dfa96c6f
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py. - Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface. - Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors. - Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
103 lines
2.5 KiB
Systemverilog
103 lines
2.5 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module i2s_send (
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input logic clk_i,
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input logic rst_n_i,
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input logic sclk_pos_i,
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input logic sclk_fall_i,
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input logic lrck_i,
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input logic bitmode_i,
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input logic [23:0] data_i,
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output logic dacdat_o,
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output logic done_o
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);
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logic s_lrck_dely_d, s_lrck_dely_q;
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logic s_lrck_trg;
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logic [4:0] s_bit_cnt_d, s_bit_cnt_q;
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logic [4:0] s_bit_num;
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logic [23:0] s_xfer_data_d, s_xfer_data_q;
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logic s_dacdat_d, s_dacdat_q;
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assign s_bit_num = bitmode_i ? 5'd23 : 5'd15;
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assign s_lrck_trg = lrck_i ^ s_lrck_dely_q;
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assign dacdat_o = s_dacdat_q;
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assign done_o = s_bit_cnt_q == s_bit_num;
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assign s_lrck_dely_d = lrck_i;
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dffer #(1) u_lrck_dely_dffer (
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clk_i,
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rst_n_i,
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sclk_pos_i,
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s_lrck_dely_d,
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s_lrck_dely_q
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);
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always_comb begin
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s_bit_cnt_d = s_bit_cnt_q;
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if (s_lrck_trg) s_bit_cnt_d = '0;
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else begin
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if (s_bit_cnt_q < s_bit_num) begin
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s_bit_cnt_d = s_bit_cnt_q + 1'b1;
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end
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end
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end
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dffer #(5) u_bit_cnt_dffer (
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clk_i,
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rst_n_i,
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sclk_pos_i,
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s_bit_cnt_d,
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s_bit_cnt_q
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);
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always_comb begin
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s_xfer_data_d = s_xfer_data_q;
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if (s_lrck_trg) begin
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s_xfer_data_d = data_i;
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end else if (s_bit_cnt_q < s_bit_num) begin
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if (bitmode_i) begin
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s_xfer_data_d = {s_xfer_data_q[22:0], 1'b0};
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end else begin
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s_xfer_data_d[23:16] = s_xfer_data_q[23:16];
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s_xfer_data_d[15:0] = {s_xfer_data_q[14:0], 1'b0};
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end
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end
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end
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dffer #(24) u_xfer_data_dffer (
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clk_i,
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rst_n_i,
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sclk_pos_i,
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s_xfer_data_d,
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s_xfer_data_q
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);
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always_comb begin
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s_dacdat_d = s_dacdat_q;
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if (s_bit_cnt_q <= s_bit_num) begin
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if (bitmode_i) s_dacdat_d = s_xfer_data_q[23];
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else s_dacdat_d = s_xfer_data_q[15];
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end
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end
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dffer #(1) u_dacdat_dffer (
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clk_i,
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rst_n_i,
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sclk_fall_i,
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s_dacdat_d,
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s_dacdat_q
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);
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endmodule
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