mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
c5dfa96c6f
- Replaced instances of nmi_if with rib_if in sysctrl_fault_tb.sv, test_dma.py, test_gpio_user_mux.py, test_memory_map.py, test_performance_log.py, test_script_tools.py, test_sdram.py, test_soc_topology.py, test_sta_constraints.py, and test_user_extensions.py. - Updated test cases to reflect changes from NMI to RIB, ensuring all references and assertions are consistent with the new interface. - Adjusted memory map and performance log tests to validate RIB-specific configurations and behaviors. - Ensured that all relevant file paths and definitions are updated to maintain functionality and correctness across the test suite.
92 lines
2.7 KiB
Systemverilog
92 lines
2.7 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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module gpio_user_formal_design (
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input logic clk_i,
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output logic rst_n_i,
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output logic f_past_valid,
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output logic rib_valid,
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output logic [31:0] rib_addr,
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output logic [31:0] rib_wdata,
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output logic [ 3:0] rib_wstrb,
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output logic rib_ready,
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output logic [31:0] gpio_di,
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output logic [31:0] gpio_oe,
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output logic [31:0] gpio_do,
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output logic [31:0] user_di,
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output logic [31:0] user_oe,
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output logic [31:0] user_do,
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output logic [31:0] user_sel,
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output logic [31:0] user_lock,
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output logic [31:0] user_handoff,
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output logic [31:0] user_status,
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output logic [31:0] native_oe,
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output logic [31:0] native_do
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);
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rib_if rib ();
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gpio_if gpio ();
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user_gpio_if user_gpio ();
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(* anyseq *)logic f_rib_valid;
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(* anyseq *)logic [31:0] f_rib_addr;
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(* anyseq *)logic [31:0] f_rib_wdata;
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(* anyseq *)logic [ 3:0] f_rib_wstrb;
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(* anyseq *)logic [31:0] f_gpio_di;
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(* anyseq *)logic [31:0] f_alt0_do;
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(* anyseq *)logic [31:0] f_alt0_oe;
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(* anyseq *)logic [31:0] f_alt1_do;
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(* anyseq *)logic [31:0] f_alt1_oe;
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(* anyseq *)logic [31:0] f_user_do;
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(* anyseq *)logic [31:0] f_user_oe;
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assign rib.valid = f_rib_valid;
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assign rib.addr = f_rib_addr;
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assign rib.wdata = f_rib_wdata;
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assign rib.wstrb = f_rib_wstrb;
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assign gpio.di_i = f_gpio_di;
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assign gpio.alt0_do_i = f_alt0_do;
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assign gpio.alt0_oe_i = f_alt0_oe;
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assign gpio.alt1_do_i = f_alt1_do;
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assign gpio.alt1_oe_i = f_alt1_oe;
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assign user_gpio.do_o = f_user_do;
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assign user_gpio.oe_o = f_user_oe;
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assign rib_valid = rib.valid;
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assign rib_addr = rib.addr;
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assign rib_wdata = rib.wdata;
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assign rib_wstrb = rib.wstrb;
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assign rib_ready = rib.ready;
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assign gpio_di = gpio.di_i;
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assign gpio_oe = gpio.oe_o;
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assign gpio_do = gpio.do_o;
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assign user_di = user_gpio.di_i;
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assign user_oe = user_gpio.oe_o;
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assign user_do = user_gpio.do_o;
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assign user_sel = u_dut.s_gpio_user_sel_q;
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assign user_lock = u_dut.s_gpio_user_lock_q;
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assign user_handoff = u_dut.s_gpio_user_handoff_q;
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assign user_status = u_dut.s_gpio_user_status;
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assign native_oe = u_dut.s_gpio_native_oe;
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assign native_do = u_dut.s_gpio_native_out;
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rib_gpio u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.rib (rib),
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.gpio (gpio),
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.user_gpio(user_gpio)
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);
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initial begin
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rst_n_i = 1'b0;
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f_past_valid = 1'b0;
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end
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always_ff @(posedge clk_i) begin
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rst_n_i <= 1'b1;
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f_past_valid <= 1'b1;
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end
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endmodule
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