mirror of
https://github.com/retroSoC/retroSoC.git
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maksyuki
c8187284d0
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow. - Added to create a checksummed delivery archive for the Tiny LibreLane implementation. - Created for synthesis-only header of the locked IHP SRAM macro physical views. - Implemented to limit OpenSTA report enumeration for path counts. - Updated to include power pad definitions. - Enhanced to handle power pad counts and validation. - Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
53 lines
2.6 KiB
Markdown
53 lines
2.6 KiB
Markdown
# Mini LibreLane IHP130 Flows
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This directory owns the Mini product line's open-source IHP130 implementation
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entry points for two independent `retrosoc` deliverables:
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- `librelane-core` hardens `retrosoc_core`, a padless logical macro with the
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canonical external pin contract and the three USB packet SRAM macros.
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- `librelane-chip` implements the bare-die `retrosoc_asic` package-facing SoC,
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including its pad ring, bondpads, fillers, corners, seal ring, and the same
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SRAM macros.
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These are separate single-level runs. The chip flow does not consume the core
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run as a hierarchical macro, so either artifact can be developed and reviewed
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without a two-level integration dependency.
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The flow consumes the committed `configs/ci/ihp130.mk` profile, canonical SoC
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pin map, and IHP-Open-PDK revision in `dependencies/dependencies.lock.json`.
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LibreLane reads the upstream `ihp-sg13g2/libs.tech/librelane` configuration
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directly through manual-PDK mode. Generated RTL, SDC, configuration, run
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databases, reports, and final views are written below the selected
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`build/<variant>/physical/librelane/mini/{core,chip}/` directory.
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Use the LibreLane 3.0.5 environment supplied by the development shell:
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```sh
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make CONFIG=configs/ci/ihp130.mk librelane-doctor
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make CONFIG=configs/ci/ihp130.mk librelane-core
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make CONFIG=configs/ci/ihp130.mk librelane-chip
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make CONFIG=configs/ci/ihp130.mk librelane-core-package
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make CONFIG=configs/ci/ihp130.mk librelane-package
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```
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The chip target places all 111 signal pads, 80 core/IO power and ground pads,
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four corners, I/O fillers, and 70 um bondpads. It is a bare-die plan, not a
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QFN/BGA package definition. The SDC constrains the external clock at 72 MHz;
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mid-PnR timing report passes are skipped because LibreLane 3.0.5 emits 1000
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expanded paths per group, while final post-RCX multi-corner STA remains enabled.
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`PDK=GF180`, `PDK=SKY130`, and `PDK=ICS55` are intentionally rejected until
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their technology-specific LibreLane adapters, pad cells, macro collateral, and
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signoff decks are qualified. The target split is technology-neutral so those
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adapters can reuse the core/chip interface when they are ready.
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IHP SG13G2 does not currently provide pad cells implementing retroSoC's
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programmable pull-up, pull-down, or Schmitt controls. The IHP implementation
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uses input-only, 4 mA output, and 4 mA bidirectional cells; unsupported GPIO
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pad-control features must not be represented as production-qualified behavior.
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A successful open-source run is evidence for implementation development, not a
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foundry production-signoff claim. Release review still requires qualified
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foundry decks, package and bond planning, electrical/ESD review, and approved
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waivers.
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