mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
84332d4573
- Added new tests for FLAC encoding and decoding, including handling of rice parameters and partial LPC tail. - Introduced WAV PCM encoding tests to ensure correct behavior across various configurations. - Updated test cases to validate the handling of malformed FLAC files and metadata structures. - Enhanced the APU register tests to include expanded P5 profile capabilities and ensure accurate register descriptions. - Improved assertions for manifest checks in the APU release tests to validate ABI and instruction counts. - Refactored existing tests for clarity and maintainability, ensuring they align with the latest APU specifications.
739 lines
30 KiB
Python
739 lines
30 KiB
Python
"""Reference interpreter for the enabled APU-P3/P4/P5 microcode targets."""
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from __future__ import annotations
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import argparse
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import json
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from dataclasses import dataclass, field
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from pathlib import Path
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from apu_isa import (
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APUMC_ABI_V1,
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APUMC_TARGETS,
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BitstreamOpcode,
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ControlOpcode,
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EntropyOpcode,
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Entry,
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Instruction,
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InstructionClass,
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LocalOpcode,
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ScalarOpcode,
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TransportOpcode,
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parse_apumc,
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trap_detail,
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validate_instruction,
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)
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from apu_primitives import PrimitiveBam, PrimitiveFault, PrimitiveResult
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class SequencerTrap(RuntimeError):
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def __init__(self, reason: int, pc: int, instruction: Instruction, detail: int | None = None):
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self.reason = reason
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self.pc = pc
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self.instruction = instruction
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self.detail = trap_detail(reason, pc, instruction) if detail is None else detail
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super().__init__(f"APU sequencer trap {reason} at PC {pc}")
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@dataclass
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class PredicateInputs:
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input_exhausted: bool = False
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input_ready: bool = False
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output_ready: bool = False
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kernel_done: bool = False
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transport_done: bool = False
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@dataclass
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class TransportCommand:
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opcode: TransportOpcode
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destination: int
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offset: int
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count: int
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payload: bytes
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cycles: int
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@dataclass
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class TransportModel:
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input_data: bytes = b""
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output_capacity: int = 0xFFFFFFFF
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stream_output: bool = False
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latency: int = 2
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output_frame_bytes: int = 4
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input_cursor: int = 0
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output: bytearray = field(default_factory=bytearray)
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frames: int = 0
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logical_input: int = 0
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logical_output: int = 0
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result_code: int = 0
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result_stage: int = 0
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result_detail: int = 0
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events: int = 0
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pending: list[TransportCommand] = field(default_factory=list)
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completed: list[tuple[int, int]] = field(default_factory=list)
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output_commands: list[dict[str, int]] = field(default_factory=list)
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@property
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def idle(self) -> bool:
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return not self.pending
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def reset(self) -> None:
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self.input_cursor = 0
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self.output.clear()
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self.frames = 0
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self.logical_input = 0
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self.logical_output = 0
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self.result_code = 0
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self.result_stage = 0
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self.result_detail = 0
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self.events = 0
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self.pending.clear()
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self.completed.clear()
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self.output_commands.clear()
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def abort(self) -> None:
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self.pending.clear()
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self.completed.clear()
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def issue(
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self,
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instruction: Instruction,
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registers: list[int],
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entry: Entry,
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primitives: PrimitiveBam,
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) -> bool:
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opcode = TransportOpcode(instruction.opcode)
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offset = registers[instruction.src0]
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count = registers[instruction.src1]
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if opcode == TransportOpcode.INPUT_REFILL:
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if (
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count < 4
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or count > 256
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or count & 3
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or offset & 3
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or offset + count > entry.scratch_bytes
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):
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raise PrimitiveFault(11, 11, 5)
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actual = min(count, len(self.input_data) - self.input_cursor)
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needed = (actual + 3) // 4
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if any(command.opcode == TransportOpcode.INPUT_REFILL for command in self.pending):
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return False
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if len(primitives.input_fifo.words) + needed > 64:
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return False
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payload = self.input_data[self.input_cursor : self.input_cursor + actual]
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self.pending.append(
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TransportCommand(
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opcode, instruction.dst, offset, actual, payload, max(1, self.latency)
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)
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)
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return True
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if opcode in (TransportOpcode.OUTPUT_COMMIT, TransportOpcode.OUTPUT_STREAM):
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if count < 1 or count > 256 or offset & 3 or offset + count > entry.scratch_bytes:
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raise PrimitiveFault(11, 11, 5)
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if count % self.output_frame_bytes or (
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(opcode == TransportOpcode.OUTPUT_STREAM) != self.stream_output
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):
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raise PrimitiveFault(11, 11, 5)
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if not primitives.output_fifo.empty:
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raise PrimitiveFault(11, 11, 5)
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if any(
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command.opcode in (TransportOpcode.OUTPUT_COMMIT, TransportOpcode.OUTPUT_STREAM)
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for command in self.pending
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):
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return False
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if (
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opcode == TransportOpcode.OUTPUT_COMMIT
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and len(self.output) + count > self.output_capacity
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):
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raise PrimitiveFault(8, 8, 9)
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address = entry.scratch_base + offset
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payload = primitives.memory.read(address, count, entry)
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self.output_commands.append({"opcode": int(opcode), "bytes": count})
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self.pending.append(
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TransportCommand(
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opcode, instruction.dst, offset, count, payload, max(1, self.latency)
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)
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)
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return True
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if opcode == TransportOpcode.DMA_WAIT:
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if not self.idle:
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return False
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self.completed.append((instruction.dst, 0))
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elif opcode == TransportOpcode.FRAME_COMMIT:
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if (
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count != self.output_frame_bytes
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or self.logical_input + offset > self.input_cursor
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or self.logical_output + count > len(self.output)
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):
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raise PrimitiveFault(11, 11, 9)
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self.logical_input = min(0xFFFFFFFF, self.logical_input + offset)
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self.logical_output = min(0xFFFFFFFF, self.logical_output + count)
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self.frames = min(0xFFFFFFFF, self.frames + 1)
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self.completed.append((instruction.dst, 0))
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elif opcode == TransportOpcode.JOB_RESULT:
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code = offset & 0x3F
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if offset >> 6 or code > 22:
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raise PrimitiveFault(11, 11, 1)
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self.result_code = code
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self.result_stage = instruction.aux & 0xF
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self.result_detail = count
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self.completed.append((instruction.dst, 0))
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else:
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self.events |= instruction.immediate & 0x0C0
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self.completed.append((instruction.dst, 0))
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return True
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def tick(self, entry: Entry, primitives: PrimitiveBam) -> None:
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if not self.pending:
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return
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for command in self.pending:
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command.cycles -= 1
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ready = [command for command in self.pending if command.cycles == 0]
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for command in ready:
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if command.opcode == TransportOpcode.INPUT_REFILL:
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primitives.memory.write(entry.scratch_base + command.offset, command.payload, entry)
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for position in range(0, command.count, 4):
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data = command.payload[position : position + 4]
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last = self.input_cursor + position + len(data) == len(self.input_data)
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primitives.input_fifo.push(
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int.from_bytes(data.ljust(4, b"\0"), "little")
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| (len(data) << 32)
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| (int(last) << 40)
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)
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self.input_cursor += command.count
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else:
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self.output.extend(command.payload)
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context_output = entry.scratch_base + entry.scratch_bytes - 64 + 44
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primitives.memory.write(
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context_output,
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len(self.output).to_bytes(4, "little"),
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entry,
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)
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self.completed.append((command.destination, command.count))
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self.pending.remove(command)
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@dataclass
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class Machine:
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instructions: list[Instruction]
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entry: Entry
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predicate_inputs: PredicateInputs = field(default_factory=PredicateInputs)
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timeout: int = 0xFFFF
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fetch_no_retirement_cycles: int = 2
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stall_cycles: dict[int, int] = field(default_factory=dict)
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registers: list[int] = field(default_factory=lambda: [0] * 16)
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eq: bool = False
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signed_lt: bool = False
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unsigned_lt: bool = False
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pc: int = 0
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retired: int = 0
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return_stack: list[int] = field(default_factory=list)
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loops: dict[int, tuple[int, int]] = field(default_factory=dict)
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watchdog: int = 0
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trace: list[dict[str, object]] = field(default_factory=list)
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target: str = "p3"
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primitives: PrimitiveBam | None = None
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transport: TransportModel | None = None
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primitive_cycles: list[int] = field(default_factory=list)
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kernel_result: PrimitiveResult | None = field(default=None, init=False)
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kernel_fault: PrimitiveFault | None = field(default=None, init=False)
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kernel_pending_fault: PrimitiveFault | None = field(default=None, init=False)
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kernel_pending_dst: int | None = field(default=None, init=False)
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kernel_cycles_remaining: int = field(default=0, init=False)
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transport_pending_dst: set[int] = field(default_factory=set, init=False)
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transport_fault: PrimitiveFault | None = field(default=None, init=False)
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mc_abi: int = APUMC_ABI_V1
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def __post_init__(self) -> None:
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self.begin_entry(self.entry)
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@staticmethod
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def _signed(value: int) -> int:
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return value if value < 0x80000000 else value - 0x100000000
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def _predicate(self, predicate: int) -> bool:
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input_ready = self.predicate_inputs.input_ready
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output_ready = self.predicate_inputs.output_ready
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kernel_done = self.predicate_inputs.kernel_done
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input_exhausted = self.predicate_inputs.input_exhausted
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if self.target in ("p4", "p5") and self.primitives is not None:
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input_ready = not self.primitives.input_fifo.empty
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output_ready = not self.primitives.output_fifo.full
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kernel_done = self.primitives.kernel_done
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input_exhausted = (
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self.primitives.eof
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and self.primitives.input_fifo.empty
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and not self.primitives.bits
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)
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values = (
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True,
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self.eq,
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not self.eq,
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self.signed_lt,
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not self.signed_lt,
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self.unsigned_lt,
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not self.unsigned_lt,
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input_exhausted,
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input_ready,
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output_ready,
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kernel_done,
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self.transport.idle
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if self.transport is not None
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else self.predicate_inputs.transport_done,
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)
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if predicate >= len(values):
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raise SequencerTrap(1, self.pc, self.instructions[self.pc])
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return values[predicate]
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def _write(self, register: int, value: int) -> None:
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self.registers[register] = value & 0xFFFFFFFF
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def _complete_kernel(self) -> None:
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if self.kernel_pending_fault is not None:
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self.kernel_fault = self.kernel_pending_fault
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elif self.kernel_result is not None:
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for register, value in self.kernel_result.writes.items():
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self._write(register, value)
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if self.primitives is not None:
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self.primitives.kernel_done = True
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self.kernel_result = None
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self.kernel_pending_fault = None
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self.kernel_pending_dst = None
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self.kernel_cycles_remaining = 0
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def _tick_kernel(self) -> None:
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if self.kernel_pending_dst is None:
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return
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if self.kernel_cycles_remaining > 0:
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self.kernel_cycles_remaining -= 1
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if self.kernel_cycles_remaining == 0:
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self._complete_kernel()
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def _tick_transport(self) -> None:
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if self.transport is None or self.primitives is None:
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return
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try:
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self.transport.tick(self.entry, self.primitives)
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except PrimitiveFault as error:
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self.transport_fault = error
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return
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while self.transport.completed:
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register, value = self.transport.completed.pop(0)
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self._write(register, value)
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self.transport_pending_dst.discard(register)
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def _pending_dependency(self, instruction: Instruction) -> bool:
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pending_registers = set(self.transport_pending_dst)
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if self.kernel_pending_dst is not None:
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pending_registers.add(self.kernel_pending_dst)
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return any(
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self._uses_pending_register(instruction, pending) for pending in pending_registers
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)
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@staticmethod
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def _uses_pending_register(instruction: Instruction, pending: int) -> bool:
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instruction_class = instruction.instruction_class
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opcode = instruction.opcode
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if instruction_class == InstructionClass.CONTROL:
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if opcode == ControlOpcode.END:
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return True
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return opcode == ControlOpcode.LOOP_SETUP and instruction.src0 == pending
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if instruction_class == InstructionClass.SCALAR:
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if opcode == ScalarOpcode.MOV:
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return instruction.src0 == pending or instruction.dst == pending
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if opcode == ScalarOpcode.MOVI:
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return instruction.dst == pending
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if opcode == ScalarOpcode.CMP:
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return instruction.src0 == pending or instruction.src1 == pending
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if opcode == ScalarOpcode.SAT:
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return instruction.src0 == pending or instruction.dst == pending
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return (
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instruction.src0 == pending
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or instruction.src1 == pending
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or instruction.dst == pending
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)
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return True
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def begin_entry(self, entry: Entry | None = None) -> None:
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if entry is not None:
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self.entry = entry
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self.pc = self.entry.entry_pc
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self.retired = 0
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self.registers = [0] * 16
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self.eq = False
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self.signed_lt = False
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self.unsigned_lt = False
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self.return_stack.clear()
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self.loops.clear()
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self.watchdog = 0
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self.kernel_result = None
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self.kernel_fault = None
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self.kernel_pending_fault = None
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self.kernel_pending_dst = None
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self.kernel_cycles_remaining = 0
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self.transport_pending_dst.clear()
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self.transport_fault = None
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if self.primitives is not None:
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self.primitives.reset_mutable()
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if self.transport is not None:
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self.transport.reset()
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def abort(self) -> None:
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self.kernel_result = None
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self.kernel_fault = None
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self.kernel_pending_fault = None
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self.kernel_pending_dst = None
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self.kernel_cycles_remaining = 0
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self.transport_pending_dst.clear()
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self.transport_fault = None
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if self.transport is not None:
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self.transport.abort()
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self.watchdog = 0
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if self.primitives is not None:
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self.primitives.reset_mutable()
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def reset(self) -> None:
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self.begin_entry(self.entry)
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def _retire(self, instruction: Instruction, predicate_true: bool) -> None:
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self.retired += 1
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self.watchdog = 0
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self.trace.append(
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{
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"pc": self.pc,
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"instruction": f"0x{instruction.encode():016x}",
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"predicate": predicate_true,
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"retired": self.retired,
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}
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)
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def _no_retirement_cycle(
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self, instruction: Instruction, *, tick_kernel: bool = True, tick_transport: bool = True
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) -> None:
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if tick_kernel:
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self._tick_kernel()
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if tick_transport:
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self._tick_transport()
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self.watchdog += 1
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if self.timeout <= 0 or self.watchdog >= self.timeout:
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raise SequencerTrap(7, self.pc, instruction)
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def _saturate(self, value: int, width: int, signed: bool) -> int:
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width = 32 if width == 0 else width
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if signed:
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signed_value = self._signed(value)
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maximum = (1 << (width - 1)) - 1
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minimum = -(1 << (width - 1))
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return min(max(signed_value, minimum), maximum) & 0xFFFFFFFF
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return min(value, (1 << width) - 1)
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def step(self) -> bool:
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if self.pc < self.entry.first_pc or self.pc > self.entry.last_pc:
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raise SequencerTrap(2, self.pc, Instruction(0, 0))
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instruction = self.instructions[self.pc]
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self._tick_kernel()
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self._tick_transport()
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if self.kernel_fault is not None:
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fault = self.kernel_fault
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self.kernel_fault = None
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raise SequencerTrap(fault.reason, self.pc, instruction)
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if self.transport_fault is not None:
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fault = self.transport_fault
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self.transport_fault = None
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raise SequencerTrap(fault.reason, self.pc, instruction)
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try:
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validate_instruction(instruction, self.target, self.mc_abi)
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except ValueError as error:
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raise SequencerTrap(1, self.pc, instruction) from error
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if self.retired >= self.entry.max_retired:
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raise SequencerTrap(8, self.pc, instruction)
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predicate_true = self._predicate(instruction.predicate)
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if not predicate_true:
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store_last = 0x7FF if self.mc_abi == APUMC_ABI_V1 else 0xFFF
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if self.pc == self.entry.last_pc or self.pc == store_last:
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raise SequencerTrap(2, self.pc, instruction)
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self._retire(instruction, predicate_true)
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self.pc += 1
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return False
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|
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if self._pending_dependency(instruction):
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self._no_retirement_cycle(instruction, tick_kernel=False, tick_transport=False)
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return False
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|
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next_pc = self.pc + 1
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terminal = False
|
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if instruction.instruction_class == InstructionClass.CONTROL:
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opcode = ControlOpcode(instruction.opcode)
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if opcode == ControlOpcode.END:
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if self.transport is not None and not self.transport.idle:
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self._no_retirement_cycle(instruction, tick_kernel=False, tick_transport=False)
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return False
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terminal = True
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elif opcode == ControlOpcode.TRAP:
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raise SequencerTrap(10, self.pc, instruction, instruction.immediate)
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elif opcode == ControlOpcode.JUMP_FWD:
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next_pc += instruction.immediate
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elif opcode == ControlOpcode.CALL_FWD:
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if len(self.return_stack) == 4:
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raise SequencerTrap(3, self.pc, instruction)
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self.return_stack.append(next_pc)
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next_pc += instruction.immediate
|
|
elif opcode == ControlOpcode.RET:
|
|
if not self.return_stack:
|
|
raise SequencerTrap(3, self.pc, instruction)
|
|
next_pc = self.return_stack.pop()
|
|
elif opcode == ControlOpcode.LOOP_SETUP:
|
|
slot = instruction.aux & 3
|
|
count = self.registers[instruction.src0] & 0xFFFF
|
|
if slot in self.loops or count == 0 or count > self.entry.max_loop_count:
|
|
raise SequencerTrap(4, self.pc, instruction)
|
|
self.loops[slot] = (count, next_pc)
|
|
elif opcode == ControlOpcode.LOOP_BACK:
|
|
slot = instruction.aux & 3
|
|
if slot not in self.loops:
|
|
raise SequencerTrap(4, self.pc, instruction)
|
|
count, start = self.loops[slot]
|
|
target = next_pc - instruction.immediate
|
|
if target != start or target < self.entry.first_pc:
|
|
raise SequencerTrap(4, self.pc, instruction)
|
|
if count > 1:
|
|
self.loops[slot] = (count - 1, start)
|
|
next_pc = target
|
|
else:
|
|
del self.loops[slot]
|
|
elif opcode == ControlOpcode.WAIT:
|
|
ready = False
|
|
if self.primitives is not None:
|
|
ready = (
|
|
(
|
|
instruction.aux == 0
|
|
and self.transport is not None
|
|
and self.transport.idle
|
|
)
|
|
or (instruction.aux == 1 and self.primitives.kernel_done)
|
|
or (instruction.aux == 2 and not self.primitives.input_fifo.empty)
|
|
or (instruction.aux == 3 and not self.primitives.output_fifo.full)
|
|
or (
|
|
instruction.aux == 4
|
|
and self.transport is not None
|
|
and self.transport.idle
|
|
)
|
|
or (
|
|
instruction.aux == 5
|
|
and self.transport is not None
|
|
and self.transport.idle
|
|
)
|
|
)
|
|
if not ready:
|
|
self._no_retirement_cycle(instruction, tick_kernel=False, tick_transport=False)
|
|
return False
|
|
elif instruction.instruction_class == InstructionClass.SCALAR:
|
|
opcode = ScalarOpcode(instruction.opcode)
|
|
source0 = self.registers[instruction.src0]
|
|
source1 = self.registers[instruction.src1]
|
|
if opcode == ScalarOpcode.MOV:
|
|
self._write(instruction.dst, source0)
|
|
elif opcode == ScalarOpcode.MOVI:
|
|
self._write(instruction.dst, instruction.immediate)
|
|
elif opcode == ScalarOpcode.ADD:
|
|
self._write(instruction.dst, source0 + source1)
|
|
elif opcode == ScalarOpcode.SUB:
|
|
self._write(instruction.dst, source0 - source1)
|
|
elif opcode == ScalarOpcode.AND:
|
|
self._write(instruction.dst, source0 & source1)
|
|
elif opcode == ScalarOpcode.OR:
|
|
self._write(instruction.dst, source0 | source1)
|
|
elif opcode == ScalarOpcode.XOR:
|
|
self._write(instruction.dst, source0 ^ source1)
|
|
elif opcode == ScalarOpcode.SHL:
|
|
self._write(instruction.dst, source0 << (source1 & 31))
|
|
elif opcode == ScalarOpcode.SHR:
|
|
self._write(instruction.dst, source0 >> (source1 & 31))
|
|
elif opcode == ScalarOpcode.SAR:
|
|
self._write(instruction.dst, self._signed(source0) >> (source1 & 31))
|
|
elif opcode == ScalarOpcode.CMP:
|
|
self.eq = source0 == source1
|
|
self.signed_lt = self._signed(source0) < self._signed(source1)
|
|
self.unsigned_lt = source0 < source1
|
|
elif opcode in (ScalarOpcode.MIN, ScalarOpcode.MAX):
|
|
left = self._signed(source0) if instruction.aux else source0
|
|
right = self._signed(source1) if instruction.aux else source1
|
|
result = min(left, right) if opcode == ScalarOpcode.MIN else max(left, right)
|
|
self._write(instruction.dst, result)
|
|
elif opcode == ScalarOpcode.SAT:
|
|
self._write(
|
|
instruction.dst,
|
|
self._saturate(source0, instruction.aux & 0x1F, bool(instruction.aux & 0x20)),
|
|
)
|
|
elif instruction.instruction_class == InstructionClass.TRANSPORT:
|
|
if self.transport is None or self.primitives is None:
|
|
raise SequencerTrap(6, self.pc, instruction)
|
|
try:
|
|
accepted = self.transport.issue(
|
|
instruction, self.registers, self.entry, self.primitives
|
|
)
|
|
except PrimitiveFault as error:
|
|
raise SequencerTrap(error.reason, self.pc, instruction) from error
|
|
if not accepted:
|
|
self._no_retirement_cycle(instruction, tick_kernel=False, tick_transport=False)
|
|
return False
|
|
if instruction.opcode <= TransportOpcode.OUTPUT_STREAM:
|
|
self.transport_pending_dst.add(instruction.dst)
|
|
else:
|
|
self._tick_transport()
|
|
else:
|
|
if self.primitives is None:
|
|
raise SequencerTrap(6, self.pc, instruction)
|
|
if instruction.instruction_class == InstructionClass.LOCAL:
|
|
opcode = LocalOpcode(instruction.opcode)
|
|
if (opcode == LocalOpcode.FIFO_POP and self.primitives.input_fifo.empty) or (
|
|
opcode == LocalOpcode.FIFO_PUSH and self.primitives.output_fifo.full
|
|
):
|
|
self._no_retirement_cycle(instruction, tick_kernel=False, tick_transport=False)
|
|
return False
|
|
if instruction.instruction_class == InstructionClass.BITSTREAM:
|
|
opcode = BitstreamOpcode(instruction.opcode)
|
|
required = 0
|
|
if opcode in (
|
|
BitstreamOpcode.REFILL,
|
|
BitstreamOpcode.PEEK,
|
|
BitstreamOpcode.GET,
|
|
BitstreamOpcode.SKIP,
|
|
):
|
|
required = instruction.immediate & 0x3F
|
|
elif opcode == BitstreamOpcode.FRAME_SYNC:
|
|
required = instruction.aux & 0x1F
|
|
if required != 0:
|
|
self.primitives._refill(required)
|
|
if required != 0 and len(self.primitives.bits) < required and not self.primitives.eof:
|
|
self._no_retirement_cycle(instruction, tick_kernel=False, tick_transport=False)
|
|
return False
|
|
if instruction.instruction_class == InstructionClass.ENTROPY:
|
|
opcode = EntropyOpcode(instruction.opcode)
|
|
if opcode <= EntropyOpcode.HUFF_QUAD:
|
|
required = instruction.aux
|
|
elif opcode == EntropyOpcode.UNARY:
|
|
required = instruction.immediate + 1
|
|
elif opcode == EntropyOpcode.SIGN_RESTORE:
|
|
required = (
|
|
0
|
|
if self.registers[instruction.src0] == 0
|
|
else (self.registers[instruction.src1] & 0x1F) + 1
|
|
)
|
|
else:
|
|
required = 1
|
|
self.primitives._refill(required)
|
|
if len(self.primitives.bits) < required and not self.primitives.eof:
|
|
self._no_retirement_cycle(instruction, tick_kernel=False, tick_transport=False)
|
|
return False
|
|
try:
|
|
if instruction.instruction_class == InstructionClass.KERNEL:
|
|
self.primitives.kernel_done = False
|
|
result = self.primitives.execute(instruction, self.registers, self.entry)
|
|
except PrimitiveFault as error:
|
|
if instruction.instruction_class != InstructionClass.KERNEL or error.reason == 5:
|
|
raise SequencerTrap(error.reason, self.pc, instruction) from error
|
|
result = PrimitiveResult(cycles=1, kernel_done=True)
|
|
self.kernel_pending_fault = error
|
|
self.primitive_cycles.append(result.cycles)
|
|
if instruction.instruction_class == InstructionClass.KERNEL:
|
|
self.primitives.kernel_done = False
|
|
self.kernel_result = result
|
|
self.kernel_pending_dst = instruction.dst
|
|
self.kernel_cycles_remaining = max(result.cycles - 1, 0)
|
|
if self.kernel_cycles_remaining == 0:
|
|
self._complete_kernel()
|
|
else:
|
|
for register, value in result.writes.items():
|
|
self._write(register, value)
|
|
for _ in range(max(result.cycles - 1, 0)):
|
|
self._no_retirement_cycle(instruction)
|
|
|
|
self._retire(instruction, predicate_true)
|
|
if not terminal:
|
|
if next_pc < self.entry.first_pc or next_pc > self.entry.last_pc:
|
|
raise SequencerTrap(2, self.pc, instruction)
|
|
self.pc = next_pc
|
|
return terminal
|
|
|
|
def run(self) -> dict[str, object]:
|
|
fetch_required = True
|
|
while True:
|
|
if self.pc < self.entry.first_pc or self.pc > self.entry.last_pc:
|
|
raise SequencerTrap(2, self.pc, Instruction(0, 0))
|
|
instruction = self.instructions[self.pc]
|
|
if fetch_required:
|
|
for _ in range(self.fetch_no_retirement_cycles):
|
|
self._no_retirement_cycle(instruction)
|
|
remaining_stalls = self.stall_cycles.get(self.pc, 0)
|
|
while remaining_stalls > 0:
|
|
self._no_retirement_cycle(instruction)
|
|
remaining_stalls -= 1
|
|
self.stall_cycles[self.pc] = 0
|
|
retired_before = self.retired
|
|
if self.step():
|
|
break
|
|
fetch_required = self.retired != retired_before
|
|
return {
|
|
"pc": self.pc,
|
|
"retired": self.retired,
|
|
"registers": self.registers,
|
|
"trace": self.trace,
|
|
"primitive_cycles": self.primitive_cycles,
|
|
"transport": None
|
|
if self.transport is None
|
|
else {
|
|
"input_used": self.transport.input_cursor,
|
|
"output": bytes(self.transport.output).hex(),
|
|
"frames": self.transport.frames,
|
|
"result_code": self.transport.result_code,
|
|
"result_stage": self.transport.result_stage,
|
|
"result_detail": self.transport.result_detail,
|
|
"events": self.transport.events,
|
|
"output_commands": self.transport.output_commands,
|
|
},
|
|
}
|
|
|
|
|
|
def main() -> int:
|
|
parser = argparse.ArgumentParser(description=__doc__)
|
|
parser.add_argument("bundle", type=Path)
|
|
parser.add_argument("--target", choices=APUMC_TARGETS, default="p3")
|
|
parser.add_argument("--entry", type=int, choices=range(3), default=0)
|
|
parser.add_argument("--timeout", type=int, default=0xFFFF)
|
|
parser.add_argument("--input-exhausted", action="store_true")
|
|
parser.add_argument("--input-ready", action="store_true")
|
|
parser.add_argument("--output-ready", action="store_true")
|
|
parser.add_argument("--kernel-done", action="store_true")
|
|
parser.add_argument("--transport-done", action="store_true")
|
|
args = parser.parse_args()
|
|
instructions, entries, header = parse_apumc(args.bundle.read_bytes(), args.target)
|
|
inputs = PredicateInputs(
|
|
input_exhausted=args.input_exhausted,
|
|
input_ready=args.input_ready,
|
|
output_ready=args.output_ready,
|
|
kernel_done=args.kernel_done,
|
|
transport_done=args.transport_done,
|
|
)
|
|
print(
|
|
json.dumps(
|
|
Machine(
|
|
instructions,
|
|
entries[args.entry],
|
|
inputs,
|
|
args.timeout,
|
|
target=args.target,
|
|
primitives=PrimitiveBam() if args.target in ("p4", "p5") else None,
|
|
transport=TransportModel() if args.target == "p5" else None,
|
|
mc_abi=header[1],
|
|
).run(),
|
|
sort_keys=True,
|
|
)
|
|
)
|
|
return 0
|
|
|
|
|
|
if __name__ == "__main__":
|
|
raise SystemExit(main())
|