Implement the memory replacement required by chapter 3 of the OpenC906
integration manual for the Mini HP core. The eight aq_spsram_* single-port
SRAM wrappers (BHT, ICache data/tag, DCache data/dirty/tag, JTLB data/tag)
gain reviewed overrides in rtl/mini/ip_overrides/, registered in
scripts/generate_openc906.py with sha256 pins on the vendored files at the
locked revision b0c06eb1.
Each override keeps the upstream behavioral aq_f_spsram_* instance
byte-identical by default; only PDK_IHP130 + HAVE_SRAM_MACRO without
PDK_BEHAV instantiates IHP130 RM_IHPSG13_1P_* macros, stacked per manual
section 3.1.5 (depth stacks with a read-registered bank select, width
stacks, zero-padded unused write-mask bits). Macro ports map CEN/GWEN/WEN
onto A_MEN/A_WEN/A_REN/A_BM with A_DLY tied high and BIST pins tied off,
matching the tc_sram.sv convention. Committed CI profiles keep
PDK_BEHAV=YES, so their simulation results are unchanged.
The Makefile also lists the new overrides as prerequisites of the
generated-filelist stamp so editing one forces regeneration.
Evidence: directed 8-wrapper equivalence TB (behavioral vs macro, Icarus)
and the manual section 3.2 MEM_INTF suite adapted to Icarus both pass on
the macro path.
The C906 ORs the internal CLINT's hardware supervisor-timer line into
mip.STIP (aq_cp0_trap_csr.v: st_int && CLINTEE || stip_reg) and the RTL
resets mxstatus.CLINTEE to 1. Nothing ever programmed STIMECMP, and the
compare registers' 0xFFFF_FFFF reset values are not guaranteed to be
applied (the HP hold-reset produces no async negedge in Verilator, so
the regs stay zero), so st_int fires from the first cycle: the moment
the kernel enables sie.STIE in time_init, it falls into an infinite
supervisor-timer storm and the boot thread starves right after the
sched_clock print. (M-mode firmware is immune, which is why RT-Thread
and OpenSBI were unaffected.)
Probe evidence after the fix: MTIMECMP arms exactly one jiffy out
(mtime+3979 at HZ=250) and MTIP fires exactly at the compare value on a
healthy 288K-cycle cadence; the kernel boots through console init,
BogoMIPS, devtmpfs, and switches to the riscv_clocksource.
Park both compare registers explicitly at cold boot so the state is
deterministic on silicon and in simulation.
Select the HP (OpenC906) JTAG target before the LP releases it, for HP
bring-up debug sessions. Behavior-neutral when off. The knob deliberately
stays out of the variant key: debug runs are not qualification evidence,
and enabling it should not force a full Linux-bundle rebuild.
The OpenC906 user manual states mxstatus.MAEE resets to 0, but the RTL
(aq_cp0_ext_csr.v) resets it to 1. With MAEE set, S-mode page attributes
come from the T-Head extended PTE bits [63:59], which a stock mainline
kernel never programs, so every translated page is non-cacheable; the
C906 then raises a store/AMO access fault (cause 7) for any AMO on such
a page (aq_lsu_ag.v: !mmu_ca && ag_pipe_amo). The first victim was
set_cpu_online()'s amoor.d.aqrl on __cpu_online_mask, after which the
kernel entered the do_trap_break storm before its first console print.
Bare-metal Sv39 payloads proved independently that page-table walks,
loads/stores, and the bus fill path are correct (4 KiB three-level,
2 MiB megapage, high-half canonical VAs, cold fills from SDRAM after D$
eviction); the failure was purely the AMO-on-non-cacheable rule, and no
bus error response or PMP denial was observed on probes.
early_init now clears mxstatus.MAEE so translated accesses follow the
sysmap override (RAM cacheable, MMIO strong-order device) and the stock
kernel needs no T-Head PBMT errata. Evidence: directed payload passes
the full AMO battery (amoor/amoadd/amoswap/lr-sc, cold-line and
high-half-VA variants); hp-linux-sim (bounded 2 h wall) boots past
set_cpu_online, prints 'Linux version 6.12.105+', and keeps retiring
into meminit with no further traps. Userspace acceptance continues on a
longer bounded run; the target stays unqualified until it completes.
The retrosoc_hp platform registered no irqchip_init hook, so the
C906-internal PLIC (thead,c900-plic, decoded by the core BIU rather than
the SoC fabric) was never initialized before the kernel probed it. Select
FDT_IRQCHIP_PLIC and register fdt_irqchip_init: OpenSBI v1.9's
thead,c900-plic match applies the T-Head M-to-S delegation quirk that
S-mode external-interrupt delivery requires. Verified by nm on the
rebuilt fw_jump.elf (fdt_irqchip_init/fdt_irqchip_plic linked in).
hp-rtthread-sim now passes on the OpenC906 HP core with all selftest
markers (6,373,952 cycles in 542 s), exercising the internal CLINT
timer/MSWI and the internal PLIC mailbox doorbell. The RT-Thread
bring-up root-cause chain (mcor/mhcr init, sdram_axi4 and crossbar WRAP
handling) is recorded with its regression locks.
hp-linux-sim ran with a bounded 4 h wall budget (158.7 M cycles):
OpenSBI v1.9 completes on the repo-owned retrosoc_hp platform and hands
off to the kernel correctly; the kernel enters S-mode with Sv39 but
stalls in the S-mode fault path after the __cpu_online_mask store page
fault (A/D-bit emulation fixup loop), which is the current bring-up
frontier. The target stays unqualified; the synthesis-dependent gates
remain deferred to the SRAM macro swap round. Also records the latent
gap that OpenSBI never initializes the C906-internal PLIC (no
.irqchip_init), harmless for the current minimal acceptance.
The Mini HP core is the locked OpenC906 with T-Head XTheadCmo custom-0
dcache maintenance; the former rv64imafdc_zicbom_max VexiiRiscv
configuration survives only as the frozen Std-series generator asset.
Sweep the leftover wording:
- scripts/README.md gains the missing setup_openc906.py and
generate_openc906.py entries (locked source install; sha256-pinned
overrides; single compilation unit below build/).
- configs/README.md and app/README.md describe the OpenC906 core and
XTheadCmo maintenance instead of VexiiRiscv RTL generation and Zicbom.
- The npu-p5-hp-sim help line and the npu_p5_report.py emitted HP
evidence mode now say polling-xtheadcmo, matching the payload's
actual dcache.cva/iva mechanism.
The C906 resets with caches and the BPU disabled (mhcr=0) and does not
initialize the cache/predictor RAMs (aq_cp0_ext_csr.v). The upstream
reference crt0 (openc906 smart_run/tests/lib/crt0.s) invalidates them
via mcor before enabling mhcr; skipping mcor makes the core execute
through uninitialized predictor/cache state (wild control flow with no
trap), and leaving caches off makes SDRAM execution ~100x slower, which
livelocked the RT-Thread 1 kHz tick ISR before the first selftest
marker.
Apply the upstream sequence at the earliest point of both HP boot
paths: RT-Thread start.S and the OpenSBI platform early_init. MMIO
windows stay strong-order non-cacheable via the sysmap override, so
enabling the D-cache is safe. hp-rtthread-sim now passes with all
selftest markers (6,373,952 cycles in 542 s).
The OpenC906 is the first master to issue WRAP bursts (cache line fills
start at the critical word). Two latent path bugs made every such fill
fail or corrupt data:
- sdram_axi4 reconstructed the WRAP wrap-back address from the
decrementing remaining-beat count, which cannot reproduce the wrap
boundary; mid-line starts read the second half from wrong addresses.
Beat stepping now uses the registered original geometry through the
proven shared axi4_addr_gen, on both the read and write paths.
- axi4_data_crossbar burst_legal computed a WRAP burst's last address
as if it were INCR, so fills starting in the last 64 bytes of a 4 KiB
page were faulted as FaultProtocol and answered with DECERR. The WRAP
last address is now computed from the wrap boundary.
Locked by new directed cases: mid-line WRAP read/write with
address-encoded data in tests/rtl/sdram_data_tb.sv and a page-edge WRAP
read routing case in tests/rtl/axi4_data_crossbar_tb.sv. Both fail on
the pre-fix RTL and pass after; full test_axi4/test_sdram (17/17),
hp-smoke-sim, hp-rtthread-sim and the PR ci_smoke all pass with the fix.
- Adjusted slot assignments in to reflect new peripheral mappings.
- Updated to validate new OpenC906 configurations, including generator and profile checks.
- Modified to reference the new Std-series VexiiRiscv generator.
- Changed cache maintenance instructions in to align with C906 specifications.
- Revised assertions in to account for internal unit removals.
- Updated to reflect changes in peripheral interface counts and policies.
- Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
- Implemented tests for WS2812 DMA sessions and refill functionality in .
- Added a new RTL testbench for WS2812 refill functionality in .
- Enhanced AXI4 data crossbar testbench to diagnose MMIO boundaries for the Mini DMA.
- Created a new Python test suite for Tiny R2 P3 to validate firmware warnings and layout placements.
- Updated existing WS2812 tests to parameterize and check for DMA backpressure integration.
- Added support for optional files in GDS generation to handle legacy layouts.
- Introduced macro-level LVS/ERC processing to improve verification of hard macros.
- Updated STA scripts to adopt PrimeTime analysis settings from legacy flows.
- Enhanced synthesis settings to align with CX55 legacy flow, including clock gating and area optimization.
- Improved reporting functions to include detailed synthesis summaries and area metrics.
- Updated package generation script to support both TINY and MINI SOC configurations.
- Added comprehensive tests for ECO translation, timing contract generation, and constraint handling.
- Ensured compatibility with new timing contract formats and enhanced error handling for domain drift.
- Updated to include support for the ICS55 PDK, allowing for conditional source inputs and configuration checks.
- Added new test cases for the ICS55 platform, including PLL backend and GPIO readback functionality.
- Modified existing tests to accommodate changes in configuration and source input handling.
- Introduced new parameters in the testbench for better configurability.
- Ensured compatibility checks for the IHP130 and ICS55 PDKs in the feasibility script.
- Enhanced the publication tests to validate hardware changes more robustly.
- Updated tiny-soc.md to reflect the 2026-10-07 refreeze, establishing ICS55 as the default target PDK with HAVE_PLL=YES.
- Added detailed sections on final timing gate policies, PLL integration, and execution order for Tiny SoC.
- Modified soc-family-positioning.md to indicate the new default target for Tiny as ICS55/PLL while maintaining IHP130 compatibility.
- Enhanced pdk/README.md and setup.py to support the integration of the locked ICS55 PLL views, including setup commands and validation.
- Introduced tests for the ICS55 PLL dependency to ensure proper integration and validation of PLL views.
- Updated rtl/tiny/README.md to clarify the current executable baseline and the pending integration of ICS55.
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads.
- Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves.
- Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements.
- Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts.
- Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
- Introduced a new test file to validate the functionality of the Tiny baseline evidence.
- Implemented tests for CPU checksum verification, log parsing, error handling, and artifact identity checks.
- Added parameterized tests to cover various edge cases, including handling of incomplete or duplicate measurements and incorrect data.
- Ensured that the tests validate the integrity of simulation results and the retention of compiler commands after post-processing.
- Introduced the PPALite extension, approved on 2026-10-05, detailing its features such as camera-inline Y extraction, RGB565 ordering, and fixed pixel/line sampling.
- Updated the tiny-soc-verification and tiny-soc documentation to reflect the new PPALite extension, including its integration with existing DVP and DMA channels.
- Added comprehensive evidence tables for PPALite phases (PPALITE-P0 to P5) outlining required evidence and current statuses.
- Clarified the relationship between PPALite and existing SPI/PIO extensions, emphasizing that earlier results cannot qualify newly added PPALite logic.
- Enhanced the README files in the RTL directory to specify PPALite's role and requirements in the context of Tiny SoC development.
- Introduced the separately approved SPI extension (2026-10-04) for the Tiny SoC, detailing the addition of SPI0 as a master-only controller with 8/16-bit capabilities.
- Updated documentation to reflect the SPI phases (SPI-P0 to SPI-P5) and their respective requirements, including DMA V2.2 pacing and fixed-MMIO requests.
- Specified GPIO assignments for SPI functionality, including the use of previously reserved Gen1 ALT routes.
- Clarified the integration boundaries and dependencies on existing R2 and PIO-lite phases, emphasizing the need for complete implementation before qualification.
- Documented the implications of SPI integration on existing GPIO and DMA channels, ensuring no additional resources are allocated without proper validation.
- Updated the verification ledgers to track pending evidence and implementation gaps for both SPI and PIO-lite extensions.
- Updated the tiny-soc-verification.md to clarify the separation of PIO-lite as a standard-product extension, detailing its planned features and evidence requirements.
- Revised tiny-soc.md to emphasize the historical context of the R2 design freeze and the independent nature of the PIO-lite extension, including its integration requirements and phase structure.
- Added details in soc-family-positioning.md regarding the PIO-lite extension's capabilities and its distinction from the R2 performance-only approval.
- Enhanced README.md files in rtl/ip and rtl/tiny to reflect the future integration of the PIO-lite extension, specifying its features and the implications for existing RTL and DMA configurations.
- Clarified integration details for WS2812 and XPI in respective documentation.
- Updated the SOC family positioning to reflect changes in clock/reset configurations and DMA channels.
- Enhanced README files for librelane and RTL to include R2 target specifics, including execution order and peripheral contracts.
- Specified the active execution order for R2 and clarified the implications of the new architecture on performance and integration.
- Added details on the Tiny Gen1 target's shared XPI register/LUT/PHY contract and optional NSS1 PSRAM integration.
- Clarified the memory model to include optional initialized XPI NSS1 PSRAM for whole-frame data.
- Updated the edge I/O section to reflect the alternate DVP V2 camera profile and GPIO allocations.
- Revised the shared services and package specifications to align with the latest P10 refreeze.
- Enhanced the README to include P10 documentation refreeze details, emphasizing DVP V2 contract and PSRAM integration.
- Updated fault reference documentation to clarify Linux termination behavior and NPU-P6 requirements.
- Enhanced Linux runtime section with emphasis on platform setup and kernel handoff processes.
- Revised overview section to include detailed descriptions of NPU capabilities and memory configurations.
- Improved product use documentation to specify Linux rootfs behavior and acceptance checkpoints.
- Clarified reset summary to differentiate between Linux and smoke/NPU-P6 acceptance processes.
- Updated software section to reflect changes in Linux image loading and readiness protocols.
- Modified build scripts to support RV64 architecture and ensure proper ELF requirements.
- Enhanced NPU compiler to support cycle counting for RV64 and RV32 architectures.
- Added tests to validate new configurations and ensure compliance with updated publication contracts.
- Revised WS2812 documentation to clarify the shared block and integration details for Mini and Tiny targets.
- Enhanced PLL Dynamic Clock Control document to specify differences between Mini and Tiny RCU implementations.
- Updated SoC Family Positioning to reflect changes in the Gen1 product/package target, including shared IP and DMA details.
- Adjusted Tiny MCU Integration README to include new features and requirements for the 2026-09-30 P6 target, emphasizing the shared peripherals and clock specifications.
- Introduced a new maintenance reference for dependency and environment routing.
- Enhanced the feature implementation skill with migration references for behavior-preserving changes.
- Added regression and RTL migration references to support feature review processes.
- Created a new physical flow skill with detailed execution and recovery guidelines.
- Updated evals for feature implementation and review skills to include new scenarios.
- Improved the AGENTS.md and tests to reflect the new skills and references.
- Added new skills for retroSoC feature implementation and review, including YAML configurations and evaluation cases.
- Removed deprecated mini feature design and implementation skills.
- Updated documentation to reflect changes in skill names and functionalities.
- Adjusted test cases to ensure compatibility with the new skill structure and validate the presence of required files and metadata.
- Updated mailbox purpose tests to reflect new write order and sequence handling.
- Added tests to ensure Linux-ready values match LP contract and constants match Linux helper.
- Introduced tests to verify that offset changes do not hide stale Linux helpers.
- Enhanced environment tests to report current locked launcher and runtime versions.
- Added checks for SBT launcher presence in environment labels.
- Improved full diagram tests to validate storage geometry and RSA vector configurations.
- Expanded register tests to ensure crypto interrupt registers publish all events and lifecycle annotations preserve security boundaries.
- Modified script tools tests to include Vexii generation validation and updated workflow assertions.
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow.
- Added to create a checksummed delivery archive for the Tiny LibreLane implementation.
- Created for synthesis-only header of the locked IHP SRAM macro physical views.
- Implemented to limit OpenSTA report enumeration for path counts.
- Updated to include power pad definitions.
- Enhanced to handle power pad counts and validation.
- Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
- Added build_hp_rtthread.py for building the RT-Thread kernel with RV64 support.
- Updated build_hp_smoke.py to target RV64 architecture and modified output filenames.
- Modified generate_vexiiriscv.py to reflect RV64 configuration and memory management.
- Created hp_tools.py for shared utilities related to RV64 builds.
- Enhanced package_hp_boot.py to package RV64 workloads and updated versioning.
- Implemented run_hp_sim.py for executing and validating HP workloads with specific markers.
- Developed setup_hp_rtthread.py for installing RT-Thread source and environment setup.
- Updated GenerateRetroSocHp.scala to generate RV64 application cores.
- Enhanced tests for HP boot bundles, platform specifications, and tool utilities to accommodate RV64 changes.
- Adjusted test cases to validate new workload types and ensure compatibility with RV64 architecture.
- Updated test paths in to point to the new directory structure for crypto files.
- Introduced to validate firmware identity and reject stale firmware based on source changes and simulation logs.
- Enhanced to include additional memory status and control registers, ensuring alignment with RTL definitions.
- Introduced new Tiny Gen1 datasheet with waveform rendering capabilities.
- Implemented example functions for various peripherals including archinfo, clint, dma, gpio, i2c, pwm, rtc, sram, sysctrl, timer, uart, wdg, and xpi.
- Enhanced register reference parsing to accommodate Tiny-specific memory maps.
- Created a dedicated Tiny reference module to isolate Tiny publications from Mini inputs.
- Developed comprehensive tests to validate Tiny publication configurations, register inventories, and evidence claims.
- Updated RTL documentation to reflect the separation of Tiny and Mini product lines.
- Updated paths in test files to reflect new directory structure for RTL and script files.
- Changed references from rtl/mini to rtl/ip and scripts/rtl where applicable.
- Added a new test file for Tiny product isolation, ensuring independent ABI and bus acceptance.
- Enhanced tests for memory map generation and protocol contracts for Tiny architecture.
- Ensured that all tests are aligned with the latest directory structure and naming conventions.
- Introduced for independent mathematical operations and RSA fixtures.
- Implemented for testing DMA channels with AES ECB and memory interactions.
- Created to validate RSA-2048 operations and Montgomery reduction.
- Developed for testing AES and SHA vector compliance.
- Added to validate image packing, integer root calculations, and inventory checks.
- Ensured robust error handling and validation in tests to catch data corruption and recursive hierarchy issues.
- Clarified P5 capabilities including direct/ring WAV/FLAC jobs and new KWS model integration.
- Specified requirements for evidence acceptance related to P5 enhancements.
- Noted that P6 MP3 support remains deferred with emphasis on design requirements.
- Updated details on P9 refreeze requirements, including macro-backed storage and future obligations.
- Reinforced that existing system clock/reset/IRQ/resource assignments remain unchanged.
- Updated the JPEG table register bank module to use combinational logic for data handling and simplified the write logic for quantization, DC, and AC entries.
- Introduced a new function in the run_flow script to handle process termination more gracefully, including signal handling for interrupts.
- Enhanced the flow script to log peak RSS memory usage during execution.
- Modified multiple testbench files to include new storage access signals and improved the test logic for better validation of KWS and SRAM interactions.
- Updated tests to validate the new peak RSS memory logging in the flow script.
- Adjusted Yosys synthesis recipes to include timeout settings and ensure proper reporting of pre-memory synthesis outputs.
- Introduced to define the development environment and validate runtime/platform contracts.
- Enhanced with to ensure change markers adhere to publication rules.
- Updated to integrate boot acceptance checks and ensure dependencies are correctly managed.
- Added tests for environment validation, publication change scope, and CI stages to prevent regression and ensure compliance with publication standards.
- Implemented checks in to validate the presence of development environment dependencies.
- Refactored existing tests to improve coverage and ensure accurate validation of publication claims and software configurations.
- Modified waveforms.json to reflect changes in resource tracking from nine to ten positions for both resource-controller integration and reference monitor parameters.
- Enhanced dev_reference.py to include NPU sources and updated CI snapshot validation to accommodate new statuses and conclusions.
- Added example NPU implementation in npu.c for job submission and result handling.
- Updated format_reference.py to validate NPU descriptor word offsets against RTL definitions.
- Adjusted storage_reference.py to reflect changes in APU and NPU local memory configurations.
- Enhanced system_reference.py to include NPU implementation details and validate accelerator claims.
- Updated tests to reflect changes in the structure and coverage of NPU and APU components, ensuring accurate validation of configurations and claims.
- Introduced new tests in v05.py to ensure distinct handling of executable configurations and evidence for NPU and APU.
- Introduced for deterministic corpus framing, CRC checks, and regression evidence for NPU-P6.
- Added to validate NPU-P6 reference execution.
- Created a new RTL model for gate-level NPU transactions.
- Updated to instantiate and streamline the testbench.
- Enhanced with capability checks and added NPU-P6 reference contract tests.
- Modified to include in the source list and refactor rejection logic.
- Updated README.md to document new test scripts and their purposes.
- Introduced differential tests for the APU-P7 frontend profile-1 BAM to ensure consistency with ROM and generator outputs.
- Implemented concurrent decode and continuous KWS smoke tests for APU-P7 to validate system stability under load.
- Added accuracy qualification tests for APU-P7 to verify through-hardware performance against expected results.
- Created contention tests for APU-P8 to assess USB2/SDIO0/APU Gateway A interactions.
- Developed quiesced loader admission tests for APU-P8 to ensure proper handling of DMA operations.
- Added post-fault visibility tests for APU-P8 HP interconnect to confirm fault handling capabilities.
- Enhanced register parity tests to include ABI digest verification for consistency across implementations.
- Updated publication register tests to reflect changes in capability constants for P5 and P7 profiles.
- Removed unsupported fault handling from and replaced it with a test for average pooling execution.
- Updated the test for unsupported placements to validate average pooling and depthwise convolution placements.
- Introduced new tests for softmax functionality in , including parameter validation and edge cases.
- Added qualification tests to ensure rejection of common-mode numerical errors and incomplete runs in .
- Enhanced RTL tests to cover memory downsizing and kernel burst capabilities in and .
- Adjusted boot status assertions in to reflect updated expected values.
This commit includes new shell source files for the NPU, specifically:
- npu_mac_array.sv
- npu_accumulator.sv
- npu_vector.sv
- npu_requantizer.sv
These additions aim to improve the testing coverage and functionality of the NPU RTL shell.
- Introduced scoped typography rules for compact cells and emphasized labels in the SoC functional overview.
- Updated the diagram to utilize new typography settings, including size adjustments for CDC and Gateway labels.
- Implemented geometry validation for SoC diagrams to ensure proper routing and clearance between elements.
- Added comprehensive tests for geometry validation, PDF typography checks, and compact text handling.
- Created new Python modules for shared geometry and PDF-bound typography checks to streamline validation processes.
- Enhanced documentation to clarify typography requirements and routing styles for SoC diagrams.
- Added validation checks for GA2D soft reset and error handling in .
- Improved resource controller tests in to cover IRQ routing and ownership scenarios.
- Updated performance log tests in to reflect changes in GA2D features and formats.
- Introduced a new netlist transaction test for GA2D in to ensure synthesized block functionality.
- Modified publication software tests in to account for new GA2D stages.
- Adjusted script tools tests in for updated configuration values.
- Added print statements for better traceability in GA2D reference campaign tests.
This commit introduces a comprehensive set of unit tests for the NPU-P3 job execution, covering the DMA engine, job decoder, and core functionalities. The tests utilize Icarus and Verilator for simulation and include descriptor validation, fault handling, and various operational scenarios. Key features include:
- Descriptor construction and validation mirroring ABI 1.0.
- Detailed test cases for valid and invalid descriptors.
- Core testbench scenarios for various operations including convolution, pooling, and fully connected layers.
- Integration of golden model comparisons for output verification.
These tests aim to ensure robust functionality and adherence to specifications for the NPU-P3 architecture.
- Introduced to ensure consistency between RTL and C register definitions.
- Implemented exhaustive checks for offsets, scalar encodings, bit shifts, and enumerations.
- Added for shell and control-CDC unit tests using Icarus and Verilator.
- Created test cases for NPU register and control CDC functionality, verifying successful simulation outputs.
- Introduced a new SOC functional architecture diagram in .
- Updated to include instructions for the new SOC diagram, including layout and design specifications.
- Modified to activate changes related to the SOC functional overview.
- Enhanced to include new SOC architecture catalog references.
- Updated to account for the new SOC architecture diagrams in coverage checks.
- Created for validating SOC diagram specifications and ensuring compliance with design rules.
- Added tests in to validate SOC diagram structure and integrity.
- Adjusted existing tests to reflect the addition of SOC architecture coverage.
- Introduced waveform definitions for GA2D operations and exceptions in waveforms.json.
- Added a new Python module for validating CI snapshots and APU implementation details.
- Enhanced diagram coverage validation to ensure accurate reporting of circuit and layout counts.
- Updated programming reference to dynamically calculate read/write credits based on master policies.
- Implemented tests for validating CI snapshot integrity and diagram coverage consistency.
- Added example usage of GA2D fill operation in a new C source file.
- Improved error handling in software reference for IRQ count validation.
- Adjusted diagram reference to check for legacy and version-specific instruction limits.
- Introduced for comprehensive testing of the NPU vector module, covering bias preload, lane-masked accumulation, and fault conditions.
- Created to implement differential tests for NPU compute-core RTL using Icarus Verilog and Verilator, ensuring bit-exact results against a numerical oracle.
- Added to validate NPU memory and patch packer functionality, including SRAM models and various packing scenarios.
- Introduced to validate KWS and VWW locked model graphs against expected configurations, including operator sequences, tensor properties, and model integrity checks.
- Added to cover numerical profiles and validate arithmetic operations, including convolution, depthwise convolution, fully connected layers, and various tensor operations.
- Created to ensure proper setup and validation of NPU-P0 reference flow, including dataset integrity and model hash consistency.
- Implemented error handling tests for malformed buffers and model mutations to ensure robustness.
- Added information about the Mini NPU specification, including its architecture and verification requirements, to rtl/README.md.
- Included details on the frozen NPU contract and its integration considerations in rtl/mini/README.md.
feat/apu splits the instruction limit into APUMC_MAX_INSTRUCTIONS_V1/V2
with APUMC_MAX_INSTRUCTIONS aliasing the V1 value, so the committed
plain '2048' assignment the drift test mutated no longer exists. Mutate
the alias assignment instead; the drift still disagrees with the RTL
define and must be rejected.
- system-reference.json: APU RX stream tready now feeds the KWS engine
(s_kws_rx_ready) instead of a constant 0
- diagram-layouts.json: APUMC header packs the requested abi word and
entry words mask entry_pc/first_pc/last_pc for APUMC V2
- diagram-storage.json: APU control store implements the 4096-word
(32 KiB) V1.1 refreeze
- diagram-circuits.json: pre-existing GA2D master 6 missing from the two
axi4_data_crossbar master_read_limit bindings (broken on dev before
the merge)
- test_script_tools.py: pre-existing whitespace-strict SOC_SIM_TIME
assertion broken by dev's app.mk alignment change (failed on dev
before the merge); use the test's regex idiom
- Adjusted the native JPEG path to reflect one normal read and one normal write credit for master slot 6 in various documentation files, including README.md, datasheets, and programming references.
- Updated the bus programming section to clarify the admission policy and error handling for the JPEG private path.
- Enhanced the media formats and product use sections to specify the implications of the new credit structure on system integration and performance.
- Modified the RTL implementation to ensure proper credit allocation for the JPEG master in the AXI4 data crossbar.
- Updated regression tests to validate the new credit handling and ensure compliance with the updated specifications.
- Increased simulation timeout for Verilator to accommodate new testing requirements.
maksyuki