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https://github.com/retroSoC/retroSoC.git
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maksyuki
e219973c45
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine. - Updated clock and reset domain tests to include USB2 ULPI crossings. - Enhanced memory map tests to verify USB2 base addresses and performance offsets. - Modified pin map tests to ensure USB2 ULPI pins are correctly generated. - Updated SOC topology tests to account for USB2 peripherals and IRQ mappings. - Added static timing analysis constraints for USB2 clock domains. - Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine. - Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
Engineering Documentation
This directory contains repository-level engineering policy that supplements the root README and subsystem guides.
- engineering.md describes reproducible inputs, build artifacts, result policy, warning baselines, metrics, CI, and releases.
- development-environment.md describes the Docker, Nix, and manual open-source regression environments.
- misra-c-2012.md defines the MISRA C:2012 Amendment 2 baseline, scope, partial automation, and deviation process.
- rtl-coding-style.md is the normative self-owned RTL policy; rtl-coding-style-compliance.md defines its executable audit and behavior-preserving migration process.
- pll-clock-control.md describes the SYSCTRL PLL register protocol and software quiesce contract.
- hazard3-debug.md defines the management Hazard3 JTAG Debug Module integration, reset boundary, and Verilator/OpenOCD/GDB flow.
- coremark.md defines the SRAM-resident Hazard3 CoreMark quick measurement, optional standard hardware run, and structured result format.
- soc-family-positioning.md defines the planned Tiny, Mini, Std, and Pro product ladder, the implemented Mini baseline, planned product targets, claim gates, and commercial reference points.
- rib-interconnect.md defines the RIB v1 linear-burst contract, compatibility boundaries, target status, and verification.
- axi4-interconnect.md defines the active Mini SoC AXI4 subset, arbitration, target, access-control, error, and performance contract.
- axi4-sdram-performance.md records the commercial SDRAM-controller survey, the implemented retroSoC MVP, and the performance roadmap that stays inside the phase-separated 16-bit / 64 MiB contract.
- axi4-stream.md defines the DMA, I2S, and DVP AXI4-Stream data paths, PIO fallback, register controls, and backpressure contract.
- ip/dma.md defines the native-AXI4 six-channel Mini DMA direct-mode register ABI, SDK API, scheduling, error, IRQ, and stream contracts.
- ip/crypto.md records the commercial AES/SHA/RSA survey and defines the Mini SoC crypto architecture, APB/DMA ABI, security boundary, HAL, verification evidence, and commercialization roadmap.
- ip/usb2.md defines the ULPI USB 2.0 dual-role architecture, AXI4 descriptor DMA, APB4 ABI, dedicated pads, HAL, and release gates.
- ip/mini-npu.md evaluates commercial edge-AI SoCs and records the optional Mini-AI NPU architecture direction, memory constraints, software boundary, and integration prerequisites; it is not an implemented profile.
- ip/ws2812.md defines the WS2812 transmitter register ABI, timing, FIFO, interrupt, DMA, and integration contracts.
- ip/timer.md defines the dual general timer register ABI, counting modes, interrupt, debug-freeze, HAL, and verification contracts.
- ip/sysctrl.md defines the SystemCtrl register ABI, user-core lifecycle, PLL/fault/performance/RTC/test contracts, HAL, and verification.
- ip/user-ip.md defines the selectable 4 KiB user-IP window, generic HAL, extension-owned register ABI, and verification contract.
- ip/clint.md defines the standard CLINT register map, fixed timebase, RV32 access rules, interrupt behavior, and verification contract.
- ip/gpio.md defines the GPIO dual-window ABI, pad ownership, filtering, interrupts, PDK capabilities, HAL, and verification contract.
- ip/uart.md defines the UART framing, FIFO, RTS/CTS flow control, error, interrupt, DMA, HAL, and verification contracts.
- ip/i2c.md defines the dual I2C command, timing, error, recovery, DMA, HAL, and verification contracts.
- ip/i2s.md defines the I2S master register ABI, phase-separated PHY, AXI4-Stream packing, CDC, HAL, and verification contracts.
- ip/psram.md defines the four-chip ESP-PSRAM64H AXI/APB4 controller, register ABI, timing, isolation, recovery, HAL, and verification contracts.
- ip/opipsram.md defines the boot-selected OPI/xSPI and single-clock HyperBus profiles, shared digital PHY, delay-cell boundary, register ABI, central-DMA use, and commercial signoff limits.
- ip/xpi.md defines the four-slot SDR XPI V2 controller, native-AXI4 mapped windows, APB4/LUT ABI, indirect/DMA/polling modes, JTAG NOR loader, commercial survey, and verification boundary.
- ip/sdio-verification.md records the standalone SD/SDIO behavioral models, directed coverage, formal bound, and verification blockers.
- ip/spisd.md defines the SPI-mode SD host commercial survey, APB/AXI architecture, register and descriptor ABI, HAL, and product boundary; ip/spisd-verification.md records its evidence and commercial delivery gaps.
- ip/ps2.md defines the Mini SoC PS/2 APB, GPIO pad, interrupt, SDK, and managed-IP integration contract.
- The managed RTC V2 datasheet defines Epoch time, alarms, periodic wake, calibration, CDC, and software.
- The managed CRC V2 datasheet defines the programmable streaming CRC engine, APB ABI, errors, and software.
- The managed PWM V2 datasheet defines the dual-timer/four-channel LED and motor PWM controller, fault, synchronization, dead-time, carrier, fade, and capture contracts.
- soc-integration-wiring.md defines the generated pin-map workflow and SoC integration boundary.
- mini-soc-block-diagram.svg is the Mini SoC architecture overview. Its Graphviz source is mini-soc-block-diagram.dot.
Keep policy descriptions here concise and link to executable configuration as
the source of truth. Changes that alter process requirements must also update
AGENTS.md when agents need to follow them.