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maksyuki
e219973c45
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine. - Updated clock and reset domain tests to include USB2 ULPI crossings. - Enhanced memory map tests to verify USB2 base addresses and performance offsets. - Modified pin map tests to ensure USB2 ULPI pins are correctly generated. - Updated SOC topology tests to account for USB2 peripherals and IRQ mappings. - Added static timing analysis constraints for USB2 clock domains. - Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine. - Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
RIB and Experimental IP
This directory owns project RTL IP.
Self-owned IP is grouped by function: interconnect, util, memory, storage, serial, USB, multimedia, and peripheral. The Mini SoC selects active sources explicitly in rtl/mini/filelist/ip.fl, whose source order is part of the build contract.
experimental contains retained inactive RTL. It is not included by any active filelist and must not become a build dependency without an explicit integration change and matching validation.