mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
e219973c45
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine. - Updated clock and reset domain tests to include USB2 ULPI crossings. - Enhanced memory map tests to verify USB2 base addresses and performance offsets. - Modified pin map tests to ensure USB2 ULPI pins are correctly generated. - Updated SOC topology tests to account for USB2 peripherals and IRQ mappings. - Added static timing analysis constraints for USB2 clock domains. - Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine. - Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
62 lines
3.8 KiB
Systemverilog
62 lines
3.8 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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`ifndef RETROSOC_SYSCTRL_DEFINE_SVH
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`define RETROSOC_SYSCTRL_DEFINE_SVH
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`include "mmap_define.svh"
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// verilog_format: off -- preserve reviewed column alignment
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`define APB4_SYSCTRL__CORESEL `SOC_SYSCTRL_CORESEL_OFFSET
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`define APB4_SYSCTRL__IPSEL `SOC_SYSCTRL_IPSEL_OFFSET
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`define APB4_SYSCTRL__PLL_CFG `SOC_SYSCTRL_PLL_CFG_OFFSET
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`define APB4_SYSCTRL__PLL_CMD `SOC_SYSCTRL_PLL_CMD_OFFSET
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`define APB4_SYSCTRL__FAULT_STATUS `SOC_SYSCTRL_FAULT_STATUS_OFFSET
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`define APB4_SYSCTRL__FAULT_ADDR `SOC_SYSCTRL_FAULT_ADDR_OFFSET
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`define APB4_SYSCTRL__FAULT_COUNT `SOC_SYSCTRL_FAULT_COUNT_OFFSET
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`define APB4_SYSCTRL__PLL_STATUS `SOC_SYSCTRL_PLL_STATUS_OFFSET
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`define APB4_SYSCTRL__USER_CORE_RESET `SOC_SYSCTRL_USER_CORE_RESET_OFFSET
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`define APB4_SYSCTRL__USER_CORE_STATUS `SOC_SYSCTRL_USER_CORE_STATUS_OFFSET
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`define APB4_SYSCTRL__FAULT_MASTER `SOC_SYSCTRL_FAULT_MASTER_OFFSET
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`define APB4_SYSCTRL__FAULT_DETAIL `SOC_SYSCTRL_FAULT_DETAIL_OFFSET
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`define APB4_SYSCTRL__PERF_CTRL `SOC_SYSCTRL_PERF_CTRL_OFFSET
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`define APB4_SYSCTRL__PERF_MGMT_WAIT_LO `SOC_SYSCTRL_PERF_MGMT_WAIT_LO_OFFSET
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`define APB4_SYSCTRL__PERF_MGMT_WAIT_HI `SOC_SYSCTRL_PERF_MGMT_WAIT_HI_OFFSET
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`define APB4_SYSCTRL__PERF_USER_WAIT_LO `SOC_SYSCTRL_PERF_USER_WAIT_LO_OFFSET
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`define APB4_SYSCTRL__PERF_USER_WAIT_HI `SOC_SYSCTRL_PERF_USER_WAIT_HI_OFFSET
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`define APB4_SYSCTRL__PERF_DMA_WAIT_LO `SOC_SYSCTRL_PERF_DMA_WAIT_LO_OFFSET
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`define APB4_SYSCTRL__PERF_DMA_WAIT_HI `SOC_SYSCTRL_PERF_DMA_WAIT_HI_OFFSET
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`define APB4_SYSCTRL__PERF_SDIO0_WAIT_LO `SOC_SYSCTRL_PERF_SDIO0_WAIT_LO_OFFSET
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`define APB4_SYSCTRL__PERF_SDIO0_WAIT_HI `SOC_SYSCTRL_PERF_SDIO0_WAIT_HI_OFFSET
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`define APB4_SYSCTRL__PERF_SDIO1_WAIT_LO `SOC_SYSCTRL_PERF_SDIO1_WAIT_LO_OFFSET
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`define APB4_SYSCTRL__PERF_SDIO1_WAIT_HI `SOC_SYSCTRL_PERF_SDIO1_WAIT_HI_OFFSET
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`define APB4_SYSCTRL__PERF_APB4_PERIPH_WAIT_LO `SOC_SYSCTRL_PERF_APB4_PERIPH_WAIT_LO_OFFSET
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`define APB4_SYSCTRL__PERF_APB4_PERIPH_WAIT_HI `SOC_SYSCTRL_PERF_APB4_PERIPH_WAIT_HI_OFFSET
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`define APB4_SYSCTRL__PERF_APB4_SYSTEM_WAIT_LO `SOC_SYSCTRL_PERF_APB4_SYSTEM_WAIT_LO_OFFSET
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`define APB4_SYSCTRL__PERF_APB4_SYSTEM_WAIT_HI `SOC_SYSCTRL_PERF_APB4_SYSTEM_WAIT_HI_OFFSET
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`define APB4_SYSCTRL__PERF_SDRAM_WAIT_LO `SOC_SYSCTRL_PERF_SDRAM_WAIT_LO_OFFSET
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`define APB4_SYSCTRL__PERF_SDRAM_WAIT_HI `SOC_SYSCTRL_PERF_SDRAM_WAIT_HI_OFFSET
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`define APB4_SYSCTRL__PERF_PSRAM_WAIT_LO `SOC_SYSCTRL_PERF_PSRAM_WAIT_LO_OFFSET
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`define APB4_SYSCTRL__PERF_PSRAM_WAIT_HI `SOC_SYSCTRL_PERF_PSRAM_WAIT_HI_OFFSET
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`define APB4_SYSCTRL__PERF_FLASH_WAIT_LO `SOC_SYSCTRL_PERF_FLASH_WAIT_LO_OFFSET
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`define APB4_SYSCTRL__PERF_FLASH_WAIT_HI `SOC_SYSCTRL_PERF_FLASH_WAIT_HI_OFFSET
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`define APB4_SYSCTRL__TEST_STATUS `SOC_SYSCTRL_TEST_STATUS_OFFSET
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`define APB4_SYSCTRL__RTC_WAKE_STATUS `SOC_SYSCTRL_RTC_WAKE_STATUS_OFFSET
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`define APB4_SYSCTRL__PERF_USB2_WAIT_LO `SOC_SYSCTRL_PERF_USB2_WAIT_LO_OFFSET
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`define APB4_SYSCTRL__PERF_USB2_WAIT_HI `SOC_SYSCTRL_PERF_USB2_WAIT_HI_OFFSET
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`define APB4_SYSCTRL__PLL_CMD_APPLY 0
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`define APB4_SYSCTRL__PLL_CMD_CLEAR_ERROR 1
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`define APB4_SYSCTRL__FAULT_STATUS_PENDING 0
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`define APB4_SYSCTRL__PERF_CTRL_ENABLE 0
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`define APB4_SYSCTRL__PERF_CTRL_CLEAR 1
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`define APB4_SYSCTRL__PERF_CTRL_SNAPSHOT 2
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`define APB4_SYSCTRL__TEST_STATUS_PASS 0
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`define APB4_SYSCTRL__TEST_STATUS_CODE 8
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`define APB4_SYSCTRL__TEST_STATUS_VALID 31
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`define APB4_SYSCTRL__RTC_WAKE_STATUS_LIVE 0
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`define APB4_SYSCTRL__RTC_WAKE_STATUS_SEEN 1
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// verilog_format: on
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`endif
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