mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
e219973c45
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine. - Updated clock and reset domain tests to include USB2 ULPI crossings. - Enhanced memory map tests to verify USB2 base addresses and performance offsets. - Modified pin map tests to ensure USB2 ULPI pins are correctly generated. - Updated SOC topology tests to account for USB2 peripherals and IRQ mappings. - Added static timing analysis constraints for USB2 clock domains. - Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine. - Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
82 lines
3.5 KiB
Systemverilog
82 lines
3.5 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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module usb2_dma_descriptor #(
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parameter int MaxDescriptors = 256
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) (
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// verilog_format: off -- descriptor ABI ports are kept in word order
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input logic [31:0] buffer_addr_i,
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input logic [31:0] byte_length_i,
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input logic [31:0] next_addr_i,
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input logic [31:0] control_i,
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input logic [31:0] actual_length_i,
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input logic [31:0] status_i,
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// Bits 26:0 are software scheduling metadata.
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/* verilator lint_off UNUSEDSIGNAL */
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input logic [31:0] frame_i,
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/* verilator lint_on UNUSEDSIGNAL */
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input logic [31:0] reserved_i,
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input
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logic [$clog2(MaxDescriptors)-1:0] desc_index_i,
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output logic own_o,
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output logic chain_o,
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output logic end_o,
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output logic irq_o,
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output logic short_ok_o,
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output logic zero_packet_o,
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output logic valid_o,
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output usb2_pkg::usb2_desc_error_e error_o
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// verilog_format: on
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);
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logic s_control_reserved;
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logic s_runtime_dirty;
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logic s_next_required;
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logic s_last_allowed;
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logic [$clog2(MaxDescriptors):0] s_descriptor_position;
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assign own_o = control_i[usb2_pkg::USB2_DESC_OWN];
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assign chain_o = control_i[usb2_pkg::USB2_DESC_CHAIN];
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assign end_o = control_i[usb2_pkg::USB2_DESC_END];
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assign irq_o = control_i[usb2_pkg::USB2_DESC_IRQ];
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assign short_ok_o = control_i[usb2_pkg::USB2_DESC_SHORT_OK];
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assign zero_packet_o = control_i[usb2_pkg::USB2_DESC_ZERO_PACKET];
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assign s_control_reserved = (control_i[15:6] != 10'd0) || (control_i[31:24] != 8'd0);
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assign s_runtime_dirty = (actual_length_i != 32'd0) || (status_i != 32'd0);
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assign s_next_required = !end_o || chain_o;
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assign s_descriptor_position = {1'b0, desc_index_i} + 1'b1;
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assign s_last_allowed = s_descriptor_position < ($clog2(MaxDescriptors) + 1)'(MaxDescriptors);
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always_comb begin
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error_o = usb2_pkg::Usb2DescOk;
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if (!own_o) begin
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error_o = usb2_pkg::Usb2DescNotOwned;
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end else if (s_control_reserved || s_runtime_dirty || (reserved_i != 32'd0)) begin
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error_o = usb2_pkg::Usb2DescReserved;
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end else if (buffer_addr_i[1:0] != 2'b00) begin
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error_o = usb2_pkg::Usb2DescBufferAlign;
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end else if (byte_length_i == 32'd0) begin
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error_o = usb2_pkg::Usb2DescLength;
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end else if (usb2_pkg::usb2_range_wraps(buffer_addr_i, byte_length_i)) begin
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error_o = usb2_pkg::Usb2DescAddressWrap;
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end else if (s_next_required &&
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((next_addr_i[4:0] != 5'd0) || (next_addr_i[11:0] > 12'hFE0))) begin
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error_o = usb2_pkg::Usb2DescNextAlign;
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end else if (end_o ? ((next_addr_i != 32'd0) || chain_o) :
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(!chain_o || (next_addr_i == 32'd0) || !s_last_allowed)) begin
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error_o = usb2_pkg::Usb2DescChain;
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end else if (frame_i[31:27] != 5'd0) begin
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error_o = usb2_pkg::Usb2DescFrameReserved;
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end
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end
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assign valid_o = error_o == usb2_pkg::Usb2DescOk;
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`ifndef SYNTHESIS
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initial begin
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if (MaxDescriptors < 2) begin
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$fatal(1, "usb2_dma_descriptor: MaxDescriptors must be at least two");
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end
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end
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`endif
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endmodule
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