mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
e219973c45
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine. - Updated clock and reset domain tests to include USB2 ULPI crossings. - Enhanced memory map tests to verify USB2 base addresses and performance offsets. - Modified pin map tests to ensure USB2 ULPI pins are correctly generated. - Updated SOC topology tests to account for USB2 peripherals and IRQ mappings. - Added static timing analysis constraints for USB2 clock domains. - Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine. - Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
530 lines
21 KiB
Systemverilog
530 lines
21 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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module usb2_link_domain #(
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parameter int NumEndpoints = 8
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) (
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// verilog_format: off -- preserve control, CDC mailbox, stream, and status groups
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input logic clk_i,
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input logic rst_n_i,
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input logic enable_i,
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input logic phy_reset_n_i,
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input logic high_speed_i,
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input usb2_pkg::usb2_role_e active_role_i,
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input logic [6:0] device_addr_i,
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input logic [NumEndpoints-1:0][31:0] endpoint_cfg_i,
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input logic [31:0] timeout_i,
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input logic work_valid_i,
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output logic work_ready_o,
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input logic [63:0] work_data_i,
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output logic result_valid_o,
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input logic result_ready_i,
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output logic [63:0] result_data_o,
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output logic setup_valid_o,
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input logic setup_ready_i,
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output logic [63:0] setup_data_o,
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input logic fill_cmd_valid_i,
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output logic fill_cmd_ready_o,
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input logic [26:0] fill_cmd_data_i,
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input logic fill_stream_valid_i,
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output logic fill_stream_ready_o,
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input logic [36:0] fill_stream_data_i,
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input logic drain_cmd_valid_i,
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output logic drain_cmd_ready_o,
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input logic [26:0] drain_cmd_data_i,
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output logic drain_stream_valid_o,
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input logic drain_stream_ready_i,
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output logic [36:0] drain_stream_data_o,
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output logic buffer_event_valid_o,
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input logic buffer_event_ready_i,
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output logic [2:0] buffer_event_data_o,
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input logic viewport_valid_i,
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output logic viewport_ready_o,
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input logic [14:0] viewport_data_i,
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output logic viewport_resp_valid_o,
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input logic viewport_resp_ready_i,
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output logic [8:0] viewport_resp_data_o,
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output logic [1:0] line_state_o,
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output logic [1:0] vbus_state_o,
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output logic id_ground_o,
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output logic link_ready_o,
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output logic [13:0] frame_o,
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output logic transaction_busy_o,
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output logic retry_o,
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output logic protocol_error_o,
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output logic [31:0] ecc_corrected_count_o,
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output logic [31:0] ecc_uncorrectable_count_o,
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usb2_ulpi_if.dut ulpi
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// verilog_format: on
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);
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localparam logic [15:0] HighSpeedMicroframeCycles = 16'd7500;
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localparam logic [15:0] FullSpeedFrameCycles = 16'd60000;
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logic s_link_rx_start;
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logic s_link_rx_valid;
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logic [ 7:0] s_link_rx_data;
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logic s_link_rx_end;
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logic s_link_rx_err;
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logic s_link_tx_start_valid;
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logic s_link_tx_start_ready;
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logic [ 3:0] s_link_tx_pid;
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logic s_link_tx_has_data;
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logic s_link_tx_data_valid;
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logic s_link_tx_data_ready;
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logic [ 7:0] s_link_tx_data;
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logic s_link_tx_data_last;
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logic s_link_tx_done;
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logic s_link_tx_err;
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logic s_rx_payload_valid;
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logic [ 7:0] s_rx_payload_data;
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logic s_rx_packet_done;
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logic s_rx_packet_good;
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logic [ 3:0] s_rx_packet_pid;
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logic [ 6:0] s_rx_token_addr;
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logic [ 3:0] s_rx_token_endpoint;
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logic [10:0] s_rx_frame_number;
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logic [10:0] s_rx_payload_len;
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logic s_rx_pid_err;
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logic s_rx_crc_err;
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logic s_rx_framing_err;
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logic s_engine_tx_req_valid;
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logic s_engine_tx_req_ready;
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logic [ 3:0] s_engine_tx_req_pid;
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logic [10:0] s_engine_tx_req_token;
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logic [10:0] s_engine_tx_req_len;
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logic s_engine_tx_payload_valid;
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logic s_engine_tx_payload_ready;
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logic s_sie_tx_payload_ready;
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logic [ 7:0] s_engine_tx_payload_data;
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logic s_engine_tx_done;
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logic s_engine_tx_err;
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logic s_sie_tx_req_valid;
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logic s_sie_tx_req_ready;
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logic [ 3:0] s_sie_tx_req_pid;
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logic [10:0] s_sie_tx_req_token;
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logic [10:0] s_sie_tx_req_len;
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logic s_sie_tx_busy;
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logic s_sie_tx_done;
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logic s_sie_tx_err;
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logic s_transaction_busy;
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logic s_engine_protocol_err;
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logic s_store_rx_start_valid;
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logic s_store_rx_start_ready;
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logic [11:0] s_store_rx_base;
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logic [14:0] s_store_rx_limit;
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logic s_store_rx_valid;
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logic s_store_rx_ready;
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logic [ 7:0] s_store_rx_data;
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logic s_store_rx_commit;
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logic s_store_rx_cancel;
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logic s_store_rx_done;
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logic [14:0] s_store_rx_bytes;
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logic s_store_rx_overflow;
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logic s_store_tx_start_valid;
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logic s_store_tx_start_ready;
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logic [11:0] s_store_tx_base;
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logic [14:0] s_store_tx_bytes;
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logic s_store_tx_valid;
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logic s_store_tx_ready;
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logic [ 7:0] s_store_tx_data;
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logic s_store_tx_done;
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logic s_store_busy;
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logic s_store_clients_enabled;
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logic s_store_fill_start_ready;
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logic s_store_drain_start_ready;
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logic s_store_rx_start_ready_raw;
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logic s_store_tx_start_ready_raw;
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logic s_fill_done;
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logic s_fill_err;
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logic s_drain_done;
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logic s_ecc_corrected;
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logic s_ecc_uncorrectable;
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logic [15:0] s_frame_count_d, s_frame_count_q;
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logic [13:0] s_frame_d, s_frame_q;
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logic s_sof_pending_d, s_sof_pending_q;
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logic s_tx_owner_engine_d, s_tx_owner_engine_q;
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logic s_buffer_event_valid_d, s_buffer_event_valid_q;
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logic [2:0] s_buffer_event_data_d, s_buffer_event_data_q;
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logic s_view_resp_valid_d, s_view_resp_valid_q;
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logic [8:0] s_view_resp_data_d, s_view_resp_data_q;
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logic [31:0] s_ecc_corrected_count_d, s_ecc_corrected_count_q;
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logic [31:0] s_ecc_uncorrectable_count_d, s_ecc_uncorrectable_count_q;
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logic [15:0] s_frame_period;
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logic s_frame_tick;
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logic s_sof_selected;
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logic s_link_view_resp_valid;
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logic [ 7:0] s_link_view_read_data;
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logic s_link_view_err;
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assign s_frame_period = high_speed_i ? HighSpeedMicroframeCycles : FullSpeedFrameCycles;
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assign s_frame_tick = s_frame_count_q == (s_frame_period - 1'b1);
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assign s_sof_selected = s_sof_pending_q && !transaction_busy_o && !s_engine_tx_req_valid;
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assign s_sie_tx_req_valid = s_engine_tx_req_valid || s_sof_selected;
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assign s_sie_tx_req_pid = s_sof_selected ? usb2_pkg::Usb2PidSof : s_engine_tx_req_pid;
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assign s_sie_tx_req_token = s_sof_selected ? s_frame_q[13:3] : s_engine_tx_req_token;
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assign s_sie_tx_req_len = s_sof_selected ? 11'd0 : s_engine_tx_req_len;
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assign s_engine_tx_req_ready = s_sie_tx_req_ready && !s_sof_selected;
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assign s_engine_tx_payload_ready = s_tx_owner_engine_q && s_sie_tx_payload_ready;
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assign s_engine_tx_done = s_sie_tx_done && s_tx_owner_engine_q;
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assign s_engine_tx_err = s_sie_tx_err && s_tx_owner_engine_q;
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assign s_store_clients_enabled = enable_i && phy_reset_n_i;
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assign fill_cmd_ready_o = s_store_clients_enabled && s_store_fill_start_ready;
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assign drain_cmd_ready_o = s_store_clients_enabled && s_store_drain_start_ready;
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assign s_store_rx_start_ready = s_store_clients_enabled && s_store_rx_start_ready_raw;
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assign s_store_tx_start_ready = s_store_clients_enabled && s_store_tx_start_ready_raw;
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assign buffer_event_valid_o = s_buffer_event_valid_q;
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assign buffer_event_data_o = s_buffer_event_data_q;
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assign viewport_resp_valid_o = s_view_resp_valid_q;
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assign viewport_resp_data_o = s_view_resp_data_q;
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assign frame_o = s_frame_q;
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assign transaction_busy_o = s_transaction_busy || s_store_busy || s_sie_tx_busy;
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assign protocol_error_o = s_engine_protocol_err || s_rx_pid_err || s_rx_crc_err ||
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s_rx_framing_err;
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assign ecc_corrected_count_o = s_ecc_corrected_count_q;
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assign ecc_uncorrectable_count_o = s_ecc_uncorrectable_count_q;
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always_comb begin
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s_frame_count_d = s_frame_count_q;
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s_frame_d = s_frame_q;
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s_sof_pending_d = s_sof_pending_q;
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s_tx_owner_engine_d = s_tx_owner_engine_q;
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s_buffer_event_valid_d = s_buffer_event_valid_q && !buffer_event_ready_i;
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s_buffer_event_data_d = s_buffer_event_data_q;
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s_view_resp_valid_d = s_view_resp_valid_q && !viewport_resp_ready_i;
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s_view_resp_data_d = s_view_resp_data_q;
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s_ecc_corrected_count_d = s_ecc_corrected_count_q;
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s_ecc_uncorrectable_count_d = s_ecc_uncorrectable_count_q;
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if ((active_role_i == usb2_pkg::Usb2RoleHost) && enable_i && phy_reset_n_i) begin
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if (s_frame_tick) begin
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s_frame_count_d = 16'd0;
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if (high_speed_i) begin
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s_frame_d = s_frame_q + 1'b1;
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end else begin
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s_frame_d = {s_frame_q[10:0] + 1'b1, 3'd0};
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end
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s_sof_pending_d = 1'b1;
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end else begin
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s_frame_count_d = s_frame_count_q + 1'b1;
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end
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end else if ((active_role_i == usb2_pkg::Usb2RoleDevice) && enable_i && phy_reset_n_i) begin
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s_frame_count_d = 16'd0;
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s_sof_pending_d = 1'b0;
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if (s_rx_packet_done && s_rx_packet_good && (s_rx_packet_pid == usb2_pkg::Usb2PidSof)) begin
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s_frame_d = {s_rx_frame_number, 3'd0};
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end
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end else begin
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s_frame_count_d = 16'd0;
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s_frame_d = 14'd0;
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s_sof_pending_d = 1'b0;
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end
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if (s_sie_tx_req_valid && s_sie_tx_req_ready) begin
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s_tx_owner_engine_d = !s_sof_selected;
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if (s_sof_selected) begin
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s_sof_pending_d = 1'b0;
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end
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end
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if (s_sie_tx_done || s_sie_tx_err) begin
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s_tx_owner_engine_d = 1'b0;
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end
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if (s_fill_done) begin
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s_buffer_event_valid_d = 1'b1;
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s_buffer_event_data_d = {s_fill_err, 2'd0};
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end else if (s_drain_done) begin
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s_buffer_event_valid_d = 1'b1;
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s_buffer_event_data_d = 3'b001;
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end
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if (s_link_view_resp_valid) begin
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s_view_resp_valid_d = 1'b1;
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s_view_resp_data_d = {s_link_view_err, s_link_view_read_data};
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end
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if (s_ecc_corrected && !(&s_ecc_corrected_count_q)) begin
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s_ecc_corrected_count_d = s_ecc_corrected_count_q + 1'b1;
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end
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if (s_ecc_uncorrectable && !(&s_ecc_uncorrectable_count_q)) begin
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s_ecc_uncorrectable_count_d = s_ecc_uncorrectable_count_q + 1'b1;
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end
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end
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usb2_ulpi_link u_ulpi_link (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.enable_i (enable_i),
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.phy_reset_n_i (phy_reset_n_i),
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.tx_start_valid_i (s_link_tx_start_valid),
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.tx_start_ready_o (s_link_tx_start_ready),
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.tx_pid_i (s_link_tx_pid),
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.tx_has_data_i (s_link_tx_has_data),
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.tx_data_valid_i (s_link_tx_data_valid),
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.tx_data_ready_o (s_link_tx_data_ready),
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.tx_data_i (s_link_tx_data),
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.tx_data_last_i (s_link_tx_data_last),
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.tx_done_o (s_link_tx_done),
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.tx_error_o (s_link_tx_err),
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.rx_start_o (s_link_rx_start),
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.rx_valid_o (s_link_rx_valid),
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.rx_data_o (s_link_rx_data),
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.rx_end_o (s_link_rx_end),
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.rx_error_o (s_link_rx_err),
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.line_state_o (line_state_o),
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.vbus_state_o (vbus_state_o),
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.id_ground_o (id_ground_o),
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.viewport_valid_i (viewport_valid_i),
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.viewport_ready_o (viewport_ready_o),
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.viewport_write_i (viewport_data_i[14]),
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.viewport_addr_i (viewport_data_i[13:8]),
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.viewport_write_data_i(viewport_data_i[7:0]),
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.viewport_resp_valid_o(s_link_view_resp_valid),
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.viewport_read_data_o (s_link_view_read_data),
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.viewport_error_o (s_link_view_err),
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.link_ready_o (link_ready_o),
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.ulpi (ulpi)
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);
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usb2_sie_rx u_sie_rx (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.rx_start_i (s_link_rx_start),
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.rx_valid_i (s_link_rx_valid),
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.rx_data_i (s_link_rx_data),
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.rx_end_i (s_link_rx_end),
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.rx_error_i (s_link_rx_err),
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.payload_valid_o (s_rx_payload_valid),
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.payload_data_o (s_rx_payload_data),
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.packet_done_o (s_rx_packet_done),
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.packet_good_o (s_rx_packet_good),
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.packet_pid_o (s_rx_packet_pid),
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.token_addr_o (s_rx_token_addr),
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.token_endpoint_o(s_rx_token_endpoint),
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.frame_number_o (s_rx_frame_number),
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.payload_length_o(s_rx_payload_len),
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.pid_error_o (s_rx_pid_err),
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.crc_error_o (s_rx_crc_err),
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.framing_error_o (s_rx_framing_err)
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);
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usb2_sie_tx u_sie_tx (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.request_valid_i (s_sie_tx_req_valid),
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.request_ready_o (s_sie_tx_req_ready),
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.request_pid_i (s_sie_tx_req_pid),
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.request_token_i (s_sie_tx_req_token),
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.request_length_i (s_sie_tx_req_len),
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.payload_valid_i (s_engine_tx_payload_valid),
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.payload_ready_o (s_sie_tx_payload_ready),
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.payload_data_i (s_engine_tx_payload_data),
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.link_start_valid_o(s_link_tx_start_valid),
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.link_start_ready_i(s_link_tx_start_ready),
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.link_pid_o (s_link_tx_pid),
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.link_has_data_o (s_link_tx_has_data),
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.link_data_valid_o (s_link_tx_data_valid),
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.link_data_ready_i (s_link_tx_data_ready),
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.link_data_o (s_link_tx_data),
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.link_data_last_o (s_link_tx_data_last),
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.link_done_i (s_link_tx_done),
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.link_error_i (s_link_tx_err),
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.busy_o (s_sie_tx_busy),
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.done_o (s_sie_tx_done),
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.error_o (s_sie_tx_err)
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);
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usb2_transaction_engine #(
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.NumEndpoints(NumEndpoints)
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) u_transaction_engine (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.active_role_i (active_role_i),
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.device_addr_i (device_addr_i),
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.endpoint_cfg_i (endpoint_cfg_i),
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.timeout_i (timeout_i),
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.work_valid_i (work_valid_i),
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.work_ready_o (work_ready_o),
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.work_data_i (work_data_i),
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.result_valid_o (result_valid_o),
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.result_ready_i (result_ready_i),
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.result_data_o (result_data_o),
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.setup_valid_o (setup_valid_o),
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.setup_ready_i (setup_ready_i),
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.setup_data_o (setup_data_o),
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.tx_request_valid_o (s_engine_tx_req_valid),
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.tx_request_ready_i (s_engine_tx_req_ready),
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.tx_request_pid_o (s_engine_tx_req_pid),
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.tx_request_token_o (s_engine_tx_req_token),
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.tx_request_length_o (s_engine_tx_req_len),
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.tx_payload_valid_o (s_engine_tx_payload_valid),
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.tx_payload_ready_i (s_engine_tx_payload_ready),
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.tx_payload_data_o (s_engine_tx_payload_data),
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.tx_done_i (s_engine_tx_done),
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.tx_error_i (s_engine_tx_err),
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.rx_payload_valid_i (s_rx_payload_valid),
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.rx_payload_data_i (s_rx_payload_data),
|
|
.rx_packet_done_i (s_rx_packet_done),
|
|
.rx_packet_good_i (s_rx_packet_good),
|
|
.rx_packet_pid_i (s_rx_packet_pid),
|
|
.rx_token_addr_i (s_rx_token_addr),
|
|
.rx_token_endpoint_i (s_rx_token_endpoint),
|
|
.rx_payload_length_i (s_rx_payload_len),
|
|
.store_rx_start_valid_o(s_store_rx_start_valid),
|
|
.store_rx_start_ready_i(s_store_rx_start_ready),
|
|
.store_rx_base_o (s_store_rx_base),
|
|
.store_rx_limit_o (s_store_rx_limit),
|
|
.store_rx_valid_o (s_store_rx_valid),
|
|
.store_rx_ready_i (s_store_rx_ready),
|
|
.store_rx_data_o (s_store_rx_data),
|
|
.store_rx_commit_o (s_store_rx_commit),
|
|
.store_rx_cancel_o (s_store_rx_cancel),
|
|
.store_rx_done_i (s_store_rx_done),
|
|
.store_rx_bytes_i (s_store_rx_bytes),
|
|
.store_rx_overflow_i (s_store_rx_overflow),
|
|
.store_tx_start_valid_o(s_store_tx_start_valid),
|
|
.store_tx_start_ready_i(s_store_tx_start_ready),
|
|
.store_tx_base_o (s_store_tx_base),
|
|
.store_tx_bytes_o (s_store_tx_bytes),
|
|
.store_tx_valid_i (s_store_tx_valid),
|
|
.store_tx_ready_o (s_store_tx_ready),
|
|
.store_tx_data_i (s_store_tx_data),
|
|
.store_tx_done_i (s_store_tx_done),
|
|
.busy_o (s_transaction_busy),
|
|
.retry_o (retry_o),
|
|
.protocol_error_o (s_engine_protocol_err)
|
|
);
|
|
|
|
usb2_packet_store u_packet_store (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.fill_start_valid_i (fill_cmd_valid_i && s_store_clients_enabled),
|
|
.fill_start_ready_o (s_store_fill_start_ready),
|
|
.fill_base_i (fill_cmd_data_i[11:0]),
|
|
.fill_bytes_i (fill_cmd_data_i[26:12]),
|
|
.fill_valid_i (fill_stream_valid_i),
|
|
.fill_ready_o (fill_stream_ready_o),
|
|
.fill_data_i (fill_stream_data_i[31:0]),
|
|
.fill_strb_i (fill_stream_data_i[35:32]),
|
|
.fill_last_i (fill_stream_data_i[36]),
|
|
.fill_done_o (s_fill_done),
|
|
.fill_error_o (s_fill_err),
|
|
.drain_start_valid_i(drain_cmd_valid_i && s_store_clients_enabled),
|
|
.drain_start_ready_o(s_store_drain_start_ready),
|
|
.drain_base_i (drain_cmd_data_i[11:0]),
|
|
.drain_bytes_i (drain_cmd_data_i[26:12]),
|
|
.drain_valid_o (drain_stream_valid_o),
|
|
.drain_ready_i (drain_stream_ready_i),
|
|
.drain_data_o (drain_stream_data_o[31:0]),
|
|
.drain_strb_o (drain_stream_data_o[35:32]),
|
|
.drain_last_o (drain_stream_data_o[36]),
|
|
.drain_done_o (s_drain_done),
|
|
.rx_start_valid_i (s_store_rx_start_valid && s_store_clients_enabled),
|
|
.rx_start_ready_o (s_store_rx_start_ready_raw),
|
|
.rx_base_i (s_store_rx_base),
|
|
.rx_limit_i (s_store_rx_limit),
|
|
.rx_valid_i (s_store_rx_valid),
|
|
.rx_ready_o (s_store_rx_ready),
|
|
.rx_data_i (s_store_rx_data),
|
|
.rx_commit_i (s_store_rx_commit),
|
|
.rx_cancel_i (s_store_rx_cancel),
|
|
.rx_done_o (s_store_rx_done),
|
|
.rx_bytes_o (s_store_rx_bytes),
|
|
.rx_overflow_o (s_store_rx_overflow),
|
|
.tx_start_valid_i (s_store_tx_start_valid && s_store_clients_enabled),
|
|
.tx_start_ready_o (s_store_tx_start_ready_raw),
|
|
.tx_base_i (s_store_tx_base),
|
|
.tx_bytes_i (s_store_tx_bytes),
|
|
.tx_valid_o (s_store_tx_valid),
|
|
.tx_ready_i (s_store_tx_ready),
|
|
.tx_data_o (s_store_tx_data),
|
|
.tx_done_o (s_store_tx_done),
|
|
.busy_o (s_store_busy),
|
|
.ecc_corrected_o (s_ecc_corrected),
|
|
.ecc_uncorrectable_o(s_ecc_uncorrectable)
|
|
);
|
|
|
|
dffr #(
|
|
.DATA_WIDTH(16)
|
|
) u_frame_count_dffr (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_frame_count_d),
|
|
.dat_o (s_frame_count_q)
|
|
);
|
|
dffr #(
|
|
.DATA_WIDTH(14)
|
|
) u_frame_dffr (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_frame_d),
|
|
.dat_o (s_frame_q)
|
|
);
|
|
dffr #(
|
|
.DATA_WIDTH(1)
|
|
) u_sof_pending_dffr (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_sof_pending_d),
|
|
.dat_o (s_sof_pending_q)
|
|
);
|
|
dffr #(
|
|
.DATA_WIDTH(1)
|
|
) u_tx_owner_engine_dffr (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_tx_owner_engine_d),
|
|
.dat_o (s_tx_owner_engine_q)
|
|
);
|
|
dffr #(
|
|
.DATA_WIDTH(1)
|
|
) u_buffer_event_valid_dffr (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_buffer_event_valid_d),
|
|
.dat_o (s_buffer_event_valid_q)
|
|
);
|
|
dffr #(
|
|
.DATA_WIDTH(3)
|
|
) u_buffer_event_data_dffr (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_buffer_event_data_d),
|
|
.dat_o (s_buffer_event_data_q)
|
|
);
|
|
dffr #(
|
|
.DATA_WIDTH(1)
|
|
) u_view_resp_valid_dffr (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_view_resp_valid_d),
|
|
.dat_o (s_view_resp_valid_q)
|
|
);
|
|
dffr #(
|
|
.DATA_WIDTH(9)
|
|
) u_view_resp_data_dffr (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_view_resp_data_d),
|
|
.dat_o (s_view_resp_data_q)
|
|
);
|
|
dffr #(
|
|
.DATA_WIDTH(32)
|
|
) u_ecc_corrected_count_dffr (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_ecc_corrected_count_d),
|
|
.dat_o (s_ecc_corrected_count_q)
|
|
);
|
|
dffr #(
|
|
.DATA_WIDTH(32)
|
|
) u_ecc_uncorrectable_count_dffr (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_ecc_uncorrectable_count_d),
|
|
.dat_o (s_ecc_uncorrectable_count_q)
|
|
);
|
|
endmodule
|