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maksyuki
e77d7b3299
- Updated onchip_ram64_tb to increase ID_WIDTH from 6 to 7 and adjusted related write/read tasks. - Modified resource_controller_tb to accommodate an expanded resource count from 8 to 9, updating related logic signals. - Enhanced sysctrl_tb to introduce new fault handling logic for data plane faults, including additional fault validation and delivery mechanisms. - Added tests for clock and reset domains to ensure proper handling of data plane faults and their reset contracts. - Introduced new test_ga2d_platform.py to verify GA2D Phase 2 functionality, including lifecycle and recovery processes. - Updated test_soc_topology.py to ensure proper data master policies and validate GA2D integration within the system. - Enhanced sysctrl.py to ensure the fault master retains the high bit for data plane faults.
RIB and Experimental IP
This directory owns project RTL IP.
Self-owned IP is grouped by function: interconnect, util, memory, storage, serial, USB, multimedia, and peripheral. The Mini SoC selects active sources explicitly in rtl/mini/filelist/ip.fl, whose source order is part of the build contract.
experimental contains retained inactive RTL. It is not included by any active filelist and must not become a build dependency without an explicit integration change and matching validation.