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maksyuki
ed19891bf5
- Introduced Verilator and Yosys warning configurations for ICS55. - Updated RTL filelists to include functional models for ICS55. - Modified memory modules to use wire instead of logic for clock and reset signals. - Enhanced Makefile and Iverilog configurations to support ICS55. - Implemented new simulation cells for ICS55 in the tech library. - Updated regression scripts and tests to include ICS55 support. - Added functionality to prepare ICS55 liberty and simulation models. - Enhanced testbench to validate ICS55 specific components and behaviors.