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https://github.com/retroSoC/retroSoC.git
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maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
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769 B
Engineering Documentation
This directory contains repository-level engineering policy that supplements the root README and subsystem guides.
- engineering.md describes reproducible inputs, build artifacts, result policy, warning baselines, metrics, CI, and releases.
- misra-c-2012.md defines the MISRA C:2012 Amendment 2 baseline, scope, partial automation, and deviation process.
- pll-clock-control.md describes the SYSCTRL PLL register protocol and software quiesce contract.
Keep policy descriptions here concise and link to executable configuration as
the source of truth. Changes that alter process requirements must also update
AGENTS.md when agents need to follow them.