mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
fc898bc4ab
- Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.
387 lines
11 KiB
Systemverilog
387 lines
11 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module rcu (
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input logic ext_clk_i,
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input logic aud_clk_i,
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input logic ext_rst_n_i,
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`ifdef HAVE_PLL
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input logic xtal_clk_i,
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`endif
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pll_ctrl_if.rcu pll_ctrl,
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output logic sys_clk_o,
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output logic sys_rst_n_o,
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output logic aud_rst_n_o,
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output logic sys_clkdiv4_o
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);
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logic s_ext_clk_buf;
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logic s_aud_clk_buf;
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logic s_sys_clk;
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logic s_ext_rst_n_sync;
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logic s_sys_rst_n_sync;
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logic s_aud_rst_n_sync;
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logic [3:0] s_div_cnt_d, s_div_cnt_q;
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logic s_sys_clkdiv4_d, s_sys_clkdiv4_q;
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tc_clk_buf u_ext_clk_buf (
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.clk_i(ext_clk_i),
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.clk_o(s_ext_clk_buf)
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);
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tc_clk_buf u_aud_clk_buf (
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.clk_i(aud_clk_i),
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.clk_o(s_aud_clk_buf)
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);
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rst_sync #(
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.STAGE(5)
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) u_ext_rst_sync (
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.clk_i (s_ext_clk_buf),
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.rst_n_i(ext_rst_n_i),
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.rst_n_o(s_ext_rst_n_sync)
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);
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`ifdef HAVE_PLL
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logic s_xtal_clk_buf;
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logic s_pll_clk;
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logic s_pll_clk_buf;
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logic s_pll_lock;
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logic s_pll_capable;
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logic [2:0] s_pll_sel;
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logic s_pll_apply;
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logic s_select_ext_clk;
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tc_clk_buf u_xtal_buf (
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.clk_i(xtal_clk_i),
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.clk_o(s_xtal_clk_buf)
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);
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tc_pll u_tc_pll (
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.fref_i (s_xtal_clk_buf),
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.rst_n_i (s_ext_rst_n_sync),
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.cfg_sel_i (s_pll_sel),
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.cfg_apply_i (s_pll_apply),
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.pll_capable_o(s_pll_capable),
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.pll_lock_o (s_pll_lock),
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.pll_clk_o (s_pll_clk)
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);
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tc_clk_buf u_pll_clk_buf (
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.clk_i(s_pll_clk),
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.clk_o(s_pll_clk_buf)
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);
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tc_clk_switch2 u_sys_clk_switch (
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.clk0_i (s_pll_clk_buf),
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.clk1_i (s_ext_clk_buf),
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.clk_sel_i(s_select_ext_clk),
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.clk_o (s_sys_clk)
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);
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pll_rcu_controller u_pll_rcu_controller (
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.sys_clk_i (s_sys_clk),
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.sys_rst_n_i (s_sys_rst_n_sync),
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.ext_clk_i (s_ext_clk_buf),
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.ext_rst_n_i (s_ext_rst_n_sync),
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.pll_lock_i (s_pll_lock),
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.pll_capable_i (s_pll_capable),
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.pll_sel_o (s_pll_sel),
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.pll_apply_o (s_pll_apply),
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.select_ext_clk_o(s_select_ext_clk),
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.pll_ctrl (pll_ctrl)
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);
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`else
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logic s_no_pll_rsp_valid_d, s_no_pll_rsp_valid_q;
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assign s_sys_clk = s_ext_clk_buf;
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assign pll_ctrl.req_ready_i = ~s_no_pll_rsp_valid_q;
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assign pll_ctrl.rsp_active_sel_i = '0;
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assign pll_ctrl.rsp_active_valid_i = 1'b0;
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assign pll_ctrl.rsp_safe_clk_i = 1'b1;
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assign pll_ctrl.rsp_pll_lock_i = 1'b0;
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assign pll_ctrl.rsp_error_i = 2'd1;
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assign pll_ctrl.rsp_valid_i = s_no_pll_rsp_valid_q;
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assign pll_ctrl.capable_i = 1'b0;
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always_comb begin
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s_no_pll_rsp_valid_d = s_no_pll_rsp_valid_q;
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if (pll_ctrl.req_valid_o && pll_ctrl.req_ready_i) begin
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s_no_pll_rsp_valid_d = 1'b1;
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end
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if (s_no_pll_rsp_valid_q && pll_ctrl.rsp_ready_o) begin
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s_no_pll_rsp_valid_d = 1'b0;
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end
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end
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dffr #(1) u_no_pll_rsp_valid_dffr (
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s_ext_clk_buf,
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s_ext_rst_n_sync,
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s_no_pll_rsp_valid_d,
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s_no_pll_rsp_valid_q
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);
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`endif
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tc_clk_buf u_sys_clk_buf (
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.clk_i(s_sys_clk),
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.clk_o(sys_clk_o)
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);
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rst_sync #(
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.STAGE(5)
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) u_sys_rst_sync (
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.clk_i (sys_clk_o),
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.rst_n_i(ext_rst_n_i),
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.rst_n_o(s_sys_rst_n_sync)
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);
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rst_sync #(
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.STAGE(5)
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) u_aud_rst_sync (
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.clk_i (s_aud_clk_buf),
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.rst_n_i(ext_rst_n_i),
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.rst_n_o(s_aud_rst_n_sync)
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);
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assign sys_rst_n_o = s_sys_rst_n_sync;
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assign aud_rst_n_o = s_aud_rst_n_sync;
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assign sys_clkdiv4_o = s_sys_clkdiv4_q;
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assign s_div_cnt_d = (s_div_cnt_q == 4'd1) ? '0 : s_div_cnt_q + 1'b1;
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dffr #(4) u_div_cnt_dffr (
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sys_clk_o,
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sys_rst_n_o,
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s_div_cnt_d,
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s_div_cnt_q
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);
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assign s_sys_clkdiv4_d = (s_div_cnt_q == 4'd1) ? ~s_sys_clkdiv4_q : s_sys_clkdiv4_q;
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dffr #(1) u_sys_clkdiv4_dffr (
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sys_clk_o,
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sys_rst_n_o,
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s_sys_clkdiv4_d,
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s_sys_clkdiv4_q
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);
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endmodule
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module pll_rcu_controller #(
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parameter int LOCK_TIMEOUT = 1024
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) (
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input logic sys_clk_i,
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input logic sys_rst_n_i,
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input logic ext_clk_i,
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input logic ext_rst_n_i,
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input logic pll_lock_i,
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input logic pll_capable_i,
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output logic [2:0] pll_sel_o,
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output logic pll_apply_o,
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output logic select_ext_clk_o,
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pll_ctrl_if.rcu pll_ctrl
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);
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localparam logic [2:0] PLL_IDLE = 3'd0;
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localparam logic [2:0] PLL_SAFE = 3'd1;
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localparam logic [2:0] PLL_APPLY = 3'd2;
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localparam logic [2:0] PLL_WAIT_LOCK = 3'd3;
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localparam logic [2:0] PLL_SWITCH = 3'd4;
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localparam logic [2:0] PLL_RESPOND = 3'd5;
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logic [2:0] s_req_sel;
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logic s_req_valid, s_req_ready;
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logic [7:0] s_rsp_data;
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logic s_rsp_valid, s_rsp_ready;
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logic [7:0] s_rsp_sys_data;
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logic s_rsp_sys_valid;
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logic [2:0] s_state_d, s_state_q;
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logic [2:0] s_pll_sel_d, s_pll_sel_q;
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logic s_pll_apply_d, s_pll_apply_q;
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logic s_select_ext_clk_d, s_select_ext_clk_q;
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logic [15:0] s_lock_count_d, s_lock_count_q;
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logic [2:0] s_active_sel_d, s_active_sel_q;
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logic s_active_valid_d, s_active_valid_q;
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logic s_safe_clk_d, s_safe_clk_q;
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logic s_lock_d, s_lock_q;
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logic [1:0] s_error_d, s_error_q;
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logic s_rsp_valid_d, s_rsp_valid_q;
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cdc_2phase #(
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.DATA_WIDTH(3)
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) u_pll_request_cdc (
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.src_clk_i (sys_clk_i),
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.src_rst_n_i(sys_rst_n_i),
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.src_data_i (pll_ctrl.req_sel_o),
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.src_valid_i(pll_ctrl.req_valid_o),
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.src_ready_o(pll_ctrl.req_ready_i),
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.dst_clk_i (ext_clk_i),
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.dst_rst_n_i(ext_rst_n_i),
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.dst_data_o (s_req_sel),
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.dst_valid_o(s_req_valid),
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.dst_ready_i(s_req_ready)
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);
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cdc_2phase #(
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.DATA_WIDTH(8)
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) u_pll_response_cdc (
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.src_clk_i (ext_clk_i),
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.src_rst_n_i(ext_rst_n_i),
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.src_data_i (s_rsp_data),
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.src_valid_i(s_rsp_valid_q),
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.src_ready_o(s_rsp_ready),
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.dst_clk_i (sys_clk_i),
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.dst_rst_n_i(sys_rst_n_i),
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.dst_data_o (s_rsp_sys_data),
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.dst_valid_o(s_rsp_sys_valid),
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.dst_ready_i(pll_ctrl.rsp_ready_o)
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);
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assign pll_ctrl.rsp_active_sel_i = s_rsp_sys_data[2:0];
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assign pll_ctrl.rsp_active_valid_i = s_rsp_sys_data[3];
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assign pll_ctrl.rsp_safe_clk_i = s_rsp_sys_data[4];
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assign pll_ctrl.rsp_pll_lock_i = s_rsp_sys_data[5];
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assign pll_ctrl.rsp_error_i = s_rsp_sys_data[7:6];
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assign pll_ctrl.rsp_valid_i = s_rsp_sys_valid;
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assign pll_ctrl.capable_i = pll_capable_i;
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assign s_req_ready = s_state_q == PLL_IDLE;
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assign s_rsp_data = {s_error_q, s_lock_q, s_safe_clk_q, s_active_valid_q, s_active_sel_q};
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assign pll_sel_o = s_pll_sel_q;
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assign pll_apply_o = s_pll_apply_q;
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assign select_ext_clk_o = s_select_ext_clk_q;
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always_comb begin
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s_state_d = s_state_q;
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s_pll_sel_d = s_pll_sel_q;
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s_pll_apply_d = (s_state_q == PLL_APPLY) || (s_state_q == PLL_WAIT_LOCK);
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s_select_ext_clk_d = s_select_ext_clk_q;
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s_lock_count_d = s_lock_count_q;
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s_active_sel_d = s_active_sel_q;
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s_active_valid_d = s_active_valid_q;
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s_safe_clk_d = s_safe_clk_q;
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s_lock_d = s_lock_q;
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s_error_d = s_error_q;
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s_rsp_valid_d = s_rsp_valid_q;
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unique case (s_state_q)
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PLL_IDLE: begin
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if (s_req_valid) begin
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s_pll_sel_d = s_req_sel;
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s_select_ext_clk_d = 1'b1;
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s_error_d = 2'd0;
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s_state_d = PLL_SAFE;
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end
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end
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PLL_SAFE: begin
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s_select_ext_clk_d = 1'b1;
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s_safe_clk_d = 1'b1;
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s_lock_d = 1'b0;
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if (pll_capable_i) begin
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s_state_d = PLL_APPLY;
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end else begin
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s_active_valid_d = 1'b0;
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s_error_d = 2'd1;
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s_state_d = PLL_RESPOND;
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end
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end
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PLL_APPLY: begin
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s_lock_count_d = '0;
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s_state_d = PLL_WAIT_LOCK;
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end
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PLL_WAIT_LOCK: begin
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if (pll_lock_i) begin
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s_active_sel_d = s_pll_sel_q;
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s_active_valid_d = 1'b1;
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s_safe_clk_d = 1'b0;
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s_lock_d = 1'b1;
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s_error_d = 2'd0;
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s_state_d = PLL_SWITCH;
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end else if (s_lock_count_q == LOCK_TIMEOUT - 1) begin
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s_active_valid_d = 1'b0;
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s_safe_clk_d = 1'b1;
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s_lock_d = 1'b0;
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s_error_d = 2'd2;
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s_state_d = PLL_RESPOND;
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end else begin
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s_lock_count_d = s_lock_count_q + 1'b1;
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end
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end
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PLL_SWITCH: begin
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s_select_ext_clk_d = 1'b0;
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s_state_d = PLL_RESPOND;
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end
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PLL_RESPOND: begin
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s_rsp_valid_d = 1'b1;
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if (s_rsp_valid_q && s_rsp_ready) begin
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s_rsp_valid_d = 1'b0;
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s_state_d = PLL_IDLE;
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end
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end
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default: begin
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s_state_d = PLL_IDLE;
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end
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endcase
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end
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dffrc #(3, PLL_IDLE) u_state_dffrc (
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ext_clk_i,
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ext_rst_n_i,
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s_state_d,
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s_state_q
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);
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dffr #(3) u_pll_sel_dffr (
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ext_clk_i,
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ext_rst_n_i,
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s_pll_sel_d,
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s_pll_sel_q
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);
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dffr #(1) u_pll_apply_dffr (
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ext_clk_i,
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ext_rst_n_i,
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s_pll_apply_d,
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s_pll_apply_q
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);
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dffrc #(1, 1'b1) u_select_ext_clk_dffrc (
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ext_clk_i,
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ext_rst_n_i,
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s_select_ext_clk_d,
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s_select_ext_clk_q
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);
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dffr #(16) u_lock_count_dffr (
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ext_clk_i,
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ext_rst_n_i,
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s_lock_count_d,
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s_lock_count_q
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);
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dffr #(3) u_active_sel_dffr (
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ext_clk_i,
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ext_rst_n_i,
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s_active_sel_d,
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s_active_sel_q
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);
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dffr #(1) u_active_valid_dffr (
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ext_clk_i,
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ext_rst_n_i,
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s_active_valid_d,
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s_active_valid_q
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);
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dffrc #(1, 1'b1) u_safe_clk_dffrc (
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ext_clk_i,
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ext_rst_n_i,
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s_safe_clk_d,
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s_safe_clk_q
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);
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dffr #(1) u_lock_dffr (
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ext_clk_i,
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ext_rst_n_i,
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s_lock_d,
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s_lock_q
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);
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dffr #(2) u_error_dffr (
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ext_clk_i,
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ext_rst_n_i,
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s_error_d,
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s_error_q
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);
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dffr #(1) u_rsp_valid_dffr (
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ext_clk_i,
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ext_rst_n_i,
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s_rsp_valid_d,
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s_rsp_valid_q
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);
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endmodule
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