7 Commits

Include renames

Author	SHA1	Message	Date
maksyuki	fc898bc4ab	feat: add PLL controller and related testbench functionality ... - Removed legacy clock definitions and added a dynamic PLL timing template in retrosoc_pll.sdc. - Introduced a new SystemVerilog testbench (pll_ctrl_tb.sv) for the PLL controller, including clock generation, register read/write tasks, and validation of PLL configuration and timing. - Updated sysctrl_fault_tb.sv to include PLL controller interface and initialization. - Enhanced memory map tests to verify PLL configuration and status offsets. - Added tests for PLL controller dynamic reconfiguration and fallback to safe clock.	2026-07-20 22:12:17 +08:00
maksyuki	3652385ea1	feat: add register slice to bus modules to optimize timing	2026-03-24 22:56:23 +08:00
maksyuki	8a87fe0f2a	style: update license header date	2026-03-07 15:03:21 +08:00
maksyuki	10e4c8e173	feat: opt the rcu clk generate function	2026-01-09 19:50:48 +08:00
maksyuki	98360bdcce	feat: add aud clk and rst signal connect	2025-08-26 13:09:15 +08:00
maksyuki	b810468684	feat: add pll macro into SoC	2025-08-12 16:00:40 +08:00
maksyuki	6df30dc3b9	feat: mv SoC specific components into mini repo	2025-06-21 16:06:05 +08:00