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https://github.com/retroSoC/timer.git
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74 lines
2.3 KiB
Systemverilog
74 lines
2.3 KiB
Systemverilog
// Copyright (c) 2023-2024 Miao Yuchi <miaoyuchi@ict.ac.cn>
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// tmr is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`ifndef INC_TMR_DEF_SV
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`define INC_TMR_DEF_SV
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/* register mapping
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* TMR_CTRL:
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* BITS: | 31:8 | 7 | 6:4 | 3 | 2 | 1 | 0 |
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* FIELDS: | RES | EEN | ETM | IDM | EN | ETR | OVIE |
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* PERMS: | NONE | RW | RW | RW | RW | RW | RW |
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* ----------------------------------------------------
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* TMR_PSCR:
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* BITS: | 31:20 | 19:0 |
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* FIELDS: | RES | PSCR |
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* PERMS: | NONE | RW |
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* -----------------------------------------------------
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* TMR_CNT:
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* BITS: | 31:0 |
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* FIELDS: | CNT |
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* PERMS: | none |
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* -----------------------------------------------------
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* TMR_CMP:
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* BITS: | 31:0 |
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* FIELDS: | CMP |
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* PERMS: | RW |
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* -----------------------------------------------------
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* TMR_STAT:
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* BITS: | 31:1 | 0 |
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* FIELDS: | RES | OVIF |
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* PERMS: | NONE | RO |
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* -----------------------------------------------------
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*/
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// 50MHz * 1
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// min: 1/50 = 0.02us = 20ns
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// max: 2^20 / 10^8 * 2^32s = 45035996s = 521day
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// timing range: [20ns ~ 521day]
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// verilog_format: off
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`define TMR_CTRL 4'b0000 // BASEADDR + 0x00
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`define TMR_PSCR 4'b0001 // BASEADDR + 0x04
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`define TMR_CNT 4'b0010 // BASEADDR + 0x08
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`define TMR_CMP 4'b0011 // BASEADDR + 0x0C
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`define TMR_STAT 4'b0100 // BASEADDR + 0x10
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`define TMR_CTRL_ADDR {26'b0, `TMR_CTRL, 2'b00}
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`define TMR_PSCR_ADDR {26'b0, `TMR_PSCR, 2'b00}
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`define TMR_CNT_ADDR {26'b0, `TMR_CNT , 2'b00}
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`define TMR_CMP_ADDR {26'b0, `TMR_CMP , 2'b00}
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`define TMR_STAT_ADDR {26'b0, `TMR_STAT, 2'b00}
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`define TMR_CTRL_WIDTH 8
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`define TMR_PSCR_WIDTH 20
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`define TMR_CNT_WIDTH 32
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`define TMR_CMP_WIDTH 32
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`define TMR_STAT_WIDTH 1
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`define TMR_PSCR_MIN_VAL {{(`TMR_PSCR_WIDTH-2){1'b0}}, 2'd2}
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`define TMR_ETM_NONE 3'b000
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`define TMR_ETM_RISE 3'b001
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`define TMR_ETM_FALL 3'b010
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`define TMR_ETM_CLER 3'b011
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`define TMR_ETM_LOAD 3'b100
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// verilog_format: on
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`endif
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