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148 lines
4.0 KiB
Markdown
148 lines
4.0 KiB
Markdown
## Datasheet
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### Overview
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The `tmr` IP is a fully parameterised soft IP using for some timing tasks. The IP features an APB4 slave interface, fully compliant with the AMBA APB Protocol Specification v2.0.
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### Feature
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* Programmable prescaler
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* max division factor is up to 2^20
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* can be changed ongoing
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* 32-bit programmable timer counter and compare register
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* Auto reload counter
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* Multiple clock source
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* internal division clock
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* external low-speed clock
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* Multiple counter mode
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* up counting
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* down counting
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* Input capture mode support
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* 1 channel
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* rise or fall trigger
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* Maskable overflow interrupt
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* Static synchronous design
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* Full synthesizable
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### Interface
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| port name | type | description |
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|:--------- |:------------|:---------------------|
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| apb4 | interface | apb4 slave interface |
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| tmr -> | interface | timer interface |
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| `tmr.exclk_i` | input | extern periodic signal |
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| `tmr.capch_i` | input | capture input |
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| `tmr.irq_o` | output | interrupt output|
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### Register
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| name | offset | length | description |
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|:----:|:-------:|:-----: | :---------: |
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| [CTRL](#control-register) | 0x0 | 4 | control register |
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| [PSCR](#prescaler-reigster) | 0x4 | 4 | prescaler register |
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| [CNT](#counter-reigster) | 0x8 | 4 | counter register |
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| [CMP](#compare-reigster) | 0xC | 4 | compare register |
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| [STAT](#state-register) | 0x10 | 4 | state register |
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#### Control Register
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| bit | access | description |
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|:---:|:-------:| :---------: |
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| `[31:8]` | none | reserved |
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| `[7:7]` | RW | EEN |
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| `[6:4]` | RW | ETM |
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| `[3:3]` | RW | IDM |
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| `[2:2]` | RW | EN |
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| `[1:1]` | RW | ETR |
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| `[0:0]` | RW | OVIE |
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reset value: `0x0000_0000`
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* EEN: extern capture enable
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* `EEN = 1'b0`: extern capture mode disabled
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* `EEN = 1'b1`: extern capture mode enabled
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* ETM: extern trigger mode
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* `ETM = 3'b000(NONE)`: none
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* `ETM = 3'b001(RISE)`: rise edge trigger
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* `ETM = 3'b010(FALL)`: fall edge trigger
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* `ETM = 3'b011(CLER)`: clear time counter
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* `ETM = 3'b100(LOAD)`: load time counter
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* IDM: time count direction mode
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* `IDM = 1'b0`: count up
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* `IDM = 1'b1`: count down
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* EN: time counter enable
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* `EN = 1'b0`: time counter disabled
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* `EN = 1'b1`: time counter enabled
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* ETR: extern tick clock trigger
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* `ETR = 1'b0`: intern clock trigger
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* `ETR = 1'b1`: extern periodic signal trigger
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* OVIE: overflow interrupt enable
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* `OVIE = 1'b0`: overflow interrupt disabled
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* `OVIE = 1'b1`: overflow interrupt enabled
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#### Prescaler Reigster
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| bit | access | description |
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|:---:|:-------:| :---------: |
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| `[31:20]` | none | reserved |
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| `[19:0]` | RW | PSCR |
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reset value: `0x0000_0002`
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* PSCR: the 20-bit prescaler value
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#### Counter Reigster
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| bit | access | description |
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|:---:|:-------:| :---------: |
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| `[31:0]` | none | CNT |
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reset value: `0x0000_0000`
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* CNT: the 32-bit extern capture counter value
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#### Compare Reigster
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| bit | access | description |
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|:---:|:-------:| :---------: |
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| `[31:0]` | RW | CMP |
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reset value: `0x0000_0000`
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* CMP: the 32-bit compare register value
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#### State Reigster
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| bit | access | description |
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|:---:|:-------:| :---------: |
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| `[31:1]` | none | reserved |
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| `[0:0]` | RO | OVIF |
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reset value: `0x0000_0000`
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* OVIF: the overflow interrupt flag
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### Program Guide
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These registers can be accessed by 4-byte aligned read and write. C-like pseudocode for the initialization operation:
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```c
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tmr.CTRL = 0x00000000 // reset ctrl register
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while(tmr.STAT == 1); // clear irq state
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tmr.PSCR = PSCR_32_bit
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tmr.CMP = CMP_32_bit
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```
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timing mode:
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```c
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REG_CTRL.[EN, OVIE] = 1 // enable intern counter and interrupt
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// polling style
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while(tmr.STAT == 0);
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// interrupt style
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tmr_interrupt_handle() {
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tmr.CTRL.OVIE = 0 // disable interrupt
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STAT_VAL = tmr.STAT // clear interrupt flag
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... // do something
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tmr.CTRL.OVIE = 1 // enable interrupt
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}
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```
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complete driver and test codes in [driver](../driver/) dir.
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### Resoureces
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### References
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### Revision History |