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Author	SHA1	Message	Date
maksyuki	eca12213ba	style: remove unsed prefix 'uart' in if	2026-03-14 15:36:46 +08:00
maksyuki	b464c64370	fix: fix a mismatch bit width in uart module	2026-01-11 13:15:54 +08:00
maksyuki	d58070f7e4	chore: restore to the pre version for 'dfferc	2026-01-09 21:10:19 +08:00
maksyuki	38c1fb002f	fix: fix the rx elem hardware trg bug	2025-12-16 10:39:10 +08:00
maksyuki	a7e0162232	fix: fix the dfferc reg params error	2025-12-11 14:28:38 +08:00
maksyuki	e149643c44	mv uart if into new file	2025-04-20 17:05:43 +08:00
maksyuki	b1cdc76190	chore: rm inc modules impl	2025-04-20 15:49:35 +08:00
maksyuki	971e28a9b5	chore: modify license holder to author name	2024-12-14 16:50:14 +08:00
maksyuki	d215e7db45	feat: add driver and test codes	2024-08-02 16:18:17 +08:00
maksyuki	025e0a9005	fix: rm unsed reg mux func	2024-07-25 12:50:24 +08:00
maksyuki	cbc228f940	fix: fix tx push data comb assign value bug	2024-07-25 07:48:28 +08:00
maksyuki	1d57820bf7	fix: add default case in rx and tx module	2024-05-27 23:06:49 +08:00
maksyuki	3bb115e9a7	docs: fix some typos	2024-05-04 22:02:59 +08:00
maksyuki	7b002aca18	fix: fix a err whitespace	2024-04-29 21:31:26 +08:00
maksyuki	59d5cc9f93	docs: add prog guide	2024-04-29 21:29:27 +08:00
maksyuki	d11c865405	docs: use 'trans' to replace 'send'	2024-04-29 20:54:22 +08:00
maksyuki	1946783937	fix: add wr fifo full test case	2024-04-29 20:53:14 +08:00
maksyuki	aaa36cc517	feat: add tx full check codes	2024-04-29 20:09:27 +08:00
maksyuki	a85c6009dd	feat: add init datasheet	2024-04-29 15:27:19 +08:00
maksyuki	e2d78258be	fix: rm unused mux switch and fifo signals	2024-04-25 16:27:43 +08:00
maksyuki	61d2f6b145	docs: modify readme file	2024-04-23 16:10:27 +08:00
maksyuki	0e33d4465f	docs: rm unused comment	2024-02-16 21:20:56 +08:00
maksyuki	3c8605e840	docs: add state badges	2024-01-09 12:02:45 +08:00
maksyuki	a8d0aacf00	docs: modify readme file	2024-01-05 09:06:43 +08:00
maksyuki	2a91e64da2	docs: add parity statement	2024-01-04 21:18:56 +08:00
maksyuki	ecd5ba6dd9	feat: use reg with en signal to rewrite module	2024-01-04 21:18:30 +08:00
maksyuki	84e818790b	docs: modify readme file	2024-01-03 15:41:49 +08:00
maksyuki	303dbea977	feat: add send and recv simple tests	2023-11-27 21:06:51 +08:00
maksyuki	cec44ed5e0	feat: remove unused wires	2023-11-27 21:06:15 +08:00
maksyuki	7e30f15a8a	chore: add rs232 sim model in the comp script	2023-11-27 21:04:06 +08:00
maksyuki	f79e004bbb	feat: modify uart module impl	2023-11-27 16:35:00 +08:00
maksyuki	d61944ec29	feat: add all testbench files	2023-11-27 16:34:17 +08:00
maksyuki	1f5391cfa6	chore: modify comp script and ignore rule file	2023-11-27 16:33:43 +08:00
maksyuki	e7710db918	feat: add rs232 slave model and testbench	2023-11-27 14:21:16 +08:00
maksyuki	fd109c5647	feat: add fifo, tx and rx module inst	2023-11-09 13:05:21 +08:00
maksyuki	0b62c1b2f7	style: modify rstn signal name	2023-11-09 13:04:38 +08:00
maksyuki	b31d21943b	feat: add apb4 uart and rm fifo modules	2023-11-09 10:41:04 +08:00
maksyuki	afe6d242b2	feat: use one bit to statement the irq	2023-11-09 10:40:17 +08:00
maksyuki	f3eb9cb75b	feat: add uart irq module	2023-11-08 17:26:15 +08:00
maksyuki	d5c1cb6948	feaat: add fifo, rx and tx module	2023-11-08 15:48:18 +08:00
maksyuki	e53601af3f	chore: init the project	2023-11-08 15:14:43 +08:00
Miao Yuchi	a5b58c9fe8	Initial commit	2023-10-28 13:55:12 +08:00