maksyuki
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f79e004bbb
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feat: modify uart module impl
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2023-11-27 16:35:00 +08:00 |
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maksyuki
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d61944ec29
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feat: add all testbench files
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2023-11-27 16:34:17 +08:00 |
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maksyuki
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1f5391cfa6
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chore: modify comp script and ignore rule file
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2023-11-27 16:33:43 +08:00 |
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maksyuki
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e7710db918
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feat: add rs232 slave model and testbench
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2023-11-27 14:21:16 +08:00 |
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maksyuki
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fd109c5647
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feat: add fifo, tx and rx module inst
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2023-11-09 13:05:21 +08:00 |
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maksyuki
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0b62c1b2f7
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style: modify rstn signal name
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2023-11-09 13:04:38 +08:00 |
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maksyuki
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b31d21943b
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feat: add apb4 uart and rm fifo modules
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2023-11-09 10:41:04 +08:00 |
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maksyuki
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afe6d242b2
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feat: use one bit to statement the irq
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2023-11-09 10:40:17 +08:00 |
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maksyuki
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f3eb9cb75b
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feat: add uart irq module
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2023-11-08 17:26:15 +08:00 |
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maksyuki
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d5c1cb6948
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feaat: add fifo, rx and tx module
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2023-11-08 15:48:18 +08:00 |
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maksyuki
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e53601af3f
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chore: init the project
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2023-11-08 15:14:43 +08:00 |
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Miao Yuchi
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a5b58c9fe8
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Initial commit
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2023-10-28 13:55:12 +08:00 |
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