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feat: add new ip modules

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maksyuki committed 2025-01-24 15:36:23 +08:00
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rtl/ip/counter_timer.v
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/* Simple 32-bit counter-timer for ravenna. */
module counter_timer (
input resetn,
input clkin,
input [3:0] reg_val_we,
input [31:0] reg_val_di,
output [31:0] reg_val_do,
input reg_cfg_we,
input [31:0] reg_cfg_di,
output [31:0] reg_cfg_do,
input [3:0] reg_dat_we,
input [31:0] reg_dat_di,
output [31:0] reg_dat_do,
output reg irq_out
);
reg [31:0] value_cur;
reg [31:0] value_reset;
//reg irq_out;
reg enable; // Enable (start) the counter/timer
reg oneshot; // Set oneshot (1) mode or continuous (0) mode
reg updown; // Count up (1) or down (0)
reg irq_ena; // Enable interrupt on timeout
// Configuration register
assign reg_cfg_do = {28'd0, irq_ena, updown, oneshot, enable};
always @(posedge clkin or negedge resetn) begin
if (resetn == 1'b0) begin
enable <= 1'b0;
oneshot <= 1'b0;
updown <= 1'b0;
irq_ena <= 1'b0;
end else begin
if (reg_cfg_we) begin
enable <= reg_cfg_di[0];
oneshot <= reg_cfg_di[1];
updown <= reg_cfg_di[2];
irq_ena <= reg_cfg_di[3];
end
end
end
// Counter/timer reset value register
assign reg_val_do = value_reset;
always @(posedge clkin or negedge resetn) begin
if (resetn == 1'b0) begin
value_reset <= 32'd0;
end else begin
if (reg_val_we[3]) value_reset <= reg_val_di[31:24];
if (reg_val_we[2]) value_reset <= reg_val_di[23:16];
if (reg_val_we[1]) value_reset <= reg_val_di[15:8];
if (reg_val_we[0]) value_reset <= reg_val_di[7:0];
end
end
assign reg_dat_do = value_cur;
// Counter/timer current value register and timer implementation
always @(posedge clkin or negedge resetn) begin
if (resetn == 1'b0) begin
value_cur <= 32'd0;
irq_out <= 1'b0;
end else begin
if (reg_dat_we != 4'b0000) begin
if (reg_dat_we[3] == 1'b1) value_cur[31:24] <= reg_dat_di[31:24];
if (reg_dat_we[2] == 1'b1) value_cur[23:16] <= reg_dat_di[23:16];
if (reg_dat_we[1] == 1'b1) value_cur[15:8] <= reg_dat_di[15:8];
if (reg_dat_we[0] == 1'b1) value_cur[7:0] <= reg_dat_di[7:0];
end else if (enable == 1'b1) begin
if (updown == 1'b1) begin
if (value_cur == value_reset) begin
if (oneshot != 1'b1) begin
value_cur <= 32'd0;
end
irq_out <= irq_ena;
end else begin
value_cur <= value_cur + 1; // count up
irq_out <= 1'b0;
end
end else begin
if (value_cur == 32'd0) begin
if (oneshot != 1'b1) begin
value_cur <= value_reset;
end
irq_out <= irq_ena;
end else begin
value_cur <= value_cur - 1; // count down
irq_out <= 1'b0;
end
end
end else begin
irq_out <= 1'b0;
end
end
end
endmodule
rtl/ip/i2c_master_bit_ctrl.v
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/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master bit-controller ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_bit_ctrl.v,v 1.14 2009-01-20 10:25:29 rherveille Exp $
//
// $Date: 2009-01-20 10:25:29 $
// $Revision: 1.14 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: $
// Revision 1.14 2009/01/20 10:25:29 rherveille
// Added clock synchronization logic
// Fixed slave_wait signal
//
// Revision 1.13 2009/01/19 20:29:26 rherveille
// Fixed cr[0] register width
// Fixed ! usage instead of ~
// Fixed bit controller parameter width to 18bits
//
// Revision 1.12 2006/09/04 09:08:13 rherveille
// fixed short scl high pulse after clock stretch
// fixed slave model not returning correct '(n)ack' signal
//
// Revision 1.11 2004/05/07 11:02:26 rherveille
// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
//
// Revision 1.10 2003/08/09 07:01:33 rherveille
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
// Fixed a potential bug in the byte controller's host-acknowledge generation.
//
// Revision 1.9 2003/03/10 14:26:37 rherveille
// Fixed cmd_ack generation item (no bug).
//
// Revision 1.8 2003/02/05 00:06:10 rherveille
// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
//
// Revision 1.7 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.6 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.5 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.4 2002/10/30 18:10:07 rherveille
// Fixed some reported minor start/stop generation timing issuess.
//
// Revision 1.3 2002/06/15 07:37:03 rherveille
// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
//
// Revision 1.2 2001/11/05 11:59:25 rherveille
// Fixed wb_ack_o generation bug.
// Fixed bug in the byte_controller statemachine.
// Added headers.
//
//
/////////////////////////////////////
// Bit controller section
/////////////////////////////////////
//
// Translate simple commands into SCL/SDA transitions
// Each command has 5 states, A/B/C/D/idle
//
// start: SCL ~~~~~~~~~~\____
// SDA ~~~~~~~~\______
// x | A | B | C | D | i
//
// repstart SCL ____/~~~~\___
// SDA __/~~~\______
// x | A | B | C | D | i
//
// stop SCL ____/~~~~~~~~
// SDA ==\____/~~~~~
// x | A | B | C | D | i
//
//- write SCL ____/~~~~\____
// SDA ==X=========X=
// x | A | B | C | D | i
//
//- read SCL ____/~~~~\____
// SDA XXXX=====XXXX
// x | A | B | C | D | i
//
// Timing: Normal mode Fast mode
///////////////////////////////////////////////////////////////////////
// Fscl 100KHz 400KHz
// Th_scl 4.0us 0.6us High period of SCL
// Tl_scl 4.7us 1.3us Low period of SCL
// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
// Tsu:sto 4.0us 0.6us setup time for a stop conditon
// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
//
`include "i2c_master_defines.v"
module i2c_master_bit_ctrl (
input clk, // system clock
input nReset, // asynchronous active low reset
input ena, // core enable signal
input [15:0] clk_cnt, // clock prescale value
input [ 3:0] cmd, // command (from byte controller)
output reg cmd_ack, // command complete acknowledge
output reg busy, // i2c bus busy
output reg al, // i2c bus arbitration lost
input din,
output reg dout,
input scl_i, // i2c clock line input
output scl_o, // i2c clock line output
output reg scl_oen, // i2c clock line output enable (active low)
input sda_i, // i2c data line input
output sda_o, // i2c data line output
output reg sda_oen // i2c data line output enable (active low)
);
//
// variable declarations
//
reg [ 1:0] cSCL, cSDA; // capture SCL and SDA
reg [ 2:0] fSCL, fSDA; // SCL and SDA filter inputs
reg sSCL, sSDA; // filtered and synchronized SCL and SDA inputs
reg dSCL, dSDA; // delayed versions of sSCL and sSDA
reg dscl_oen; // delayed scl_oen
reg sda_chk; // check SDA output (Multi-master arbitration)
reg clk_en; // clock generation signals
reg slave_wait; // slave inserts wait states
reg [15:0] cnt; // clock divider counter (synthesis)
reg [13:0] filter_cnt; // clock divider for filter
// state machine variable
reg [17:0] c_state;
//
// module body
//
// whenever the slave is not ready it can delay the cycle by pulling SCL low
// delay scl_oen
always @(posedge clk)
dscl_oen <= scl_oen;
// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
// slave_wait remains asserted until the slave releases SCL
always @(posedge clk or negedge nReset)
if (!nReset) slave_wait <= 1'b0;
else slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
// master drives SCL high, but another master pulls it low
// master start counting down its low cycle now (clock synchronization)
wire scl_sync = dSCL & ~sSCL & scl_oen;
// generate clk enable signal
always @(posedge clk or negedge nReset)
if (~nReset)
begin
cnt <= 16'h0;
clk_en <= 1'b1;
end
else if (~|cnt || !ena || scl_sync)
begin
cnt <= clk_cnt;
clk_en <= 1'b1;
end
else if (slave_wait)
begin
cnt <= cnt;
clk_en <= 1'b0;
end
else
begin
cnt <= cnt - 16'h1;
clk_en <= 1'b0;
end
// generate bus status controller
// capture SDA and SCL
// reduce metastability risk
always @(posedge clk or negedge nReset)
if (!nReset)
begin
cSCL <= 2'b00;
cSDA <= 2'b00;
end
else
begin
cSCL <= {cSCL[0],scl_i};
cSDA <= {cSDA[0],sda_i};
end
// filter SCL and SDA signals; (attempt to) remove glitches
always @(posedge clk or negedge nReset)
if (!nReset ) filter_cnt <= 14'h0;
else if (!ena ) filter_cnt <= 14'h0;
else if (~|filter_cnt) filter_cnt <= clk_cnt >> 2; //16x I2C bus frequency
else filter_cnt <= filter_cnt -1;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
fSCL <= 3'b111;
fSDA <= 3'b111;
end
else if (~|filter_cnt)
begin
fSCL <= {fSCL[1:0],cSCL[1]};
fSDA <= {fSDA[1:0],cSDA[1]};
end
// generate filtered SCL and SDA signals
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sSCL <= 1'b1;
sSDA <= 1'b1;
dSCL <= 1'b1;
dSDA <= 1'b1;
end
else
begin
sSCL <= &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]);
sSDA <= &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]);
dSCL <= sSCL;
dSDA <= sSDA;
end
// detect start condition => detect falling edge on SDA while SCL is high
// detect stop condition => detect rising edge on SDA while SCL is high
reg sta_condition;
reg sto_condition;
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sta_condition <= 1'b0;
sto_condition <= 1'b0;
end
else
begin
sta_condition <= ~sSDA & dSDA & sSCL;
sto_condition <= sSDA & ~dSDA & sSCL;
end
// generate i2c bus busy signal
always @(posedge clk or negedge nReset)
if (!nReset) busy <= 1'b0;
else busy <= (sta_condition | busy) & ~sto_condition;
// generate arbitration lost signal
// aribitration lost when:
// 1) master drives SDA high, but the i2c bus is low
// 2) stop detected while not requested
reg cmd_stop;
always @(posedge clk or negedge nReset)
if (~nReset)
cmd_stop <= 1'b0;
else if (clk_en)
cmd_stop <= cmd == `I2C_CMD_STOP;
always @(posedge clk or negedge nReset)
if (~nReset)
al <= 1'b0;
else
al <= (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
// generate dout signal (store SDA on rising edge of SCL)
always @(posedge clk)
if (sSCL & ~dSCL) dout <= sSDA;
// generate statemachine
// nxt_state decoder
parameter [17:0] idle = 18'b0_0000_0000_0000_0000;
parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;
parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;
parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;
parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;
parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;
parameter [17:0] stop_a = 18'b0_0000_0000_0010_0000;
parameter [17:0] stop_b = 18'b0_0000_0000_0100_0000;
parameter [17:0] stop_c = 18'b0_0000_0000_1000_0000;
parameter [17:0] stop_d = 18'b0_0000_0001_0000_0000;
parameter [17:0] rd_a = 18'b0_0000_0010_0000_0000;
parameter [17:0] rd_b = 18'b0_0000_0100_0000_0000;
parameter [17:0] rd_c = 18'b0_0000_1000_0000_0000;
parameter [17:0] rd_d = 18'b0_0001_0000_0000_0000;
parameter [17:0] wr_a = 18'b0_0010_0000_0000_0000;
parameter [17:0] wr_b = 18'b0_0100_0000_0000_0000;
parameter [17:0] wr_c = 18'b0_1000_0000_0000_0000;
parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
c_state <= idle;
cmd_ack <= 1'b0;
scl_oen <= 1'b1;
sda_oen <= 1'b1;
sda_chk <= 1'b0;
end
else if (al)
begin
c_state <= idle;
cmd_ack <= 1'b0;
scl_oen <= 1'b1;
sda_oen <= 1'b1;
sda_chk <= 1'b0;
end
else
begin
cmd_ack <= 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
if (clk_en)
case (c_state)
// idle state
idle:
begin
case (cmd)
`I2C_CMD_START: c_state <= start_a;
`I2C_CMD_STOP: c_state <= stop_a;
`I2C_CMD_WRITE: c_state <= wr_a;
`I2C_CMD_READ: c_state <= rd_a;
default: c_state <= idle;
endcase
scl_oen <= scl_oen; // keep SCL in same state
sda_oen <= sda_oen; // keep SDA in same state
sda_chk <= 1'b0; // don't check SDA output
end
// start
start_a:
begin
c_state <= start_b;
scl_oen <= scl_oen; // keep SCL in same state
sda_oen <= 1'b1; // set SDA high
sda_chk <= 1'b0; // don't check SDA output
end
start_b:
begin
c_state <= start_c;
scl_oen <= 1'b1; // set SCL high
sda_oen <= 1'b1; // keep SDA high
sda_chk <= 1'b0; // don't check SDA output
end
start_c:
begin
c_state <= start_d;
scl_oen <= 1'b1; // keep SCL high
sda_oen <= 1'b0; // set SDA low
sda_chk <= 1'b0; // don't check SDA output
end
start_d:
begin
c_state <= start_e;
scl_oen <= 1'b1; // keep SCL high
sda_oen <= 1'b0; // keep SDA low
sda_chk <= 1'b0; // don't check SDA output
end
start_e:
begin
c_state <= idle;
cmd_ack <= 1'b1;
scl_oen <= 1'b0; // set SCL low
sda_oen <= 1'b0; // keep SDA low
sda_chk <= 1'b0; // don't check SDA output
end
// stop
stop_a:
begin
c_state <= stop_b;
scl_oen <= 1'b0; // keep SCL low
sda_oen <= 1'b0; // set SDA low
sda_chk <= 1'b0; // don't check SDA output
end
stop_b:
begin
c_state <= stop_c;
scl_oen <= 1'b1; // set SCL high
sda_oen <= 1'b0; // keep SDA low
sda_chk <= 1'b0; // don't check SDA output
end
stop_c:
begin
c_state <= stop_d;
scl_oen <= 1'b1; // keep SCL high
sda_oen <= 1'b0; // keep SDA low
sda_chk <= 1'b0; // don't check SDA output
end
stop_d:
begin
c_state <= idle;
cmd_ack <= 1'b1;
scl_oen <= 1'b1; // keep SCL high
sda_oen <= 1'b1; // set SDA high
sda_chk <= 1'b0; // don't check SDA output
end
// read
rd_a:
begin
c_state <= rd_b;
scl_oen <= 1'b0; // keep SCL low
sda_oen <= 1'b1; // tri-state SDA
sda_chk <= 1'b0; // don't check SDA output
end
rd_b:
begin
c_state <= rd_c;
scl_oen <= 1'b1; // set SCL high
sda_oen <= 1'b1; // keep SDA tri-stated
sda_chk <= 1'b0; // don't check SDA output
end
rd_c:
begin
c_state <= rd_d;
scl_oen <= 1'b1; // keep SCL high
sda_oen <= 1'b1; // keep SDA tri-stated
sda_chk <= 1'b0; // don't check SDA output
end
rd_d:
begin
c_state <= idle;
cmd_ack <= 1'b1;
scl_oen <= 1'b0; // set SCL low
sda_oen <= 1'b1; // keep SDA tri-stated
sda_chk <= 1'b0; // don't check SDA output
end
// write
wr_a:
begin
c_state <= wr_b;
scl_oen <= 1'b0; // keep SCL low
sda_oen <= din; // set SDA
sda_chk <= 1'b0; // don't check SDA output (SCL low)
end
wr_b:
begin
c_state <= wr_c;
scl_oen <= 1'b1; // set SCL high
sda_oen <= din; // keep SDA
sda_chk <= 1'b0; // don't check SDA output yet
// allow some time for SDA and SCL to settle
end
wr_c:
begin
c_state <= wr_d;
scl_oen <= 1'b1; // keep SCL high
sda_oen <= din;
sda_chk <= 1'b1; // check SDA output
end
wr_d:
begin
c_state <= idle;
cmd_ack <= 1'b1;
scl_oen <= 1'b0; // set SCL low
sda_oen <= din;
sda_chk <= 1'b0; // don't check SDA output (SCL low)
end
endcase
end
// assign scl and sda output (always gnd)
assign scl_o = 1'b0;
assign sda_o = 1'b0;
endmodule
rtl/ip/i2c_master_byte_ctrl.v
+334
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/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master byte-controller ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_byte_ctrl.v,v 1.8 2009-01-19 20:29:26 rherveille Exp $
//
// $Date: 2009-01-19 20:29:26 $
// $Revision: 1.8 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.7 2004/02/18 11:40:46 rherveille
// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
//
// Revision 1.6 2003/08/09 07:01:33 rherveille
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
// Fixed a potential bug in the byte controller's host-acknowledge generation.
//
// Revision 1.5 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.4 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.3 2001/11/05 11:59:25 rherveille
// Fixed wb_ack_o generation bug.
// Fixed bug in the byte_controller statemachine.
// Added headers.
//
`include "i2c_master_defines.v"
module i2c_master_byte_ctrl (
clk, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
//
// inputs & outputs
//
input clk; // master clock
input nReset; // synchronous active low reset
input ena; // core enable signal
input [15:0] clk_cnt; // 4x SCL
// control inputs
input start;
input stop;
input read;
input write;
input ack_in;
input [7:0] din;
// status outputs
output cmd_ack;
reg cmd_ack;
output ack_out;
reg ack_out;
output i2c_busy;
output i2c_al;
output [7:0] dout;
// I2C signals
input scl_i;
output scl_o;
output scl_oen;
input sda_i;
output sda_o;
output sda_oen;
//
// Variable declarations
//
// statemachine
parameter [4:0] ST_IDLE = 5'b0_0000;
parameter [4:0] ST_START = 5'b0_0001;
parameter [4:0] ST_READ = 5'b0_0010;
parameter [4:0] ST_WRITE = 5'b0_0100;
parameter [4:0] ST_ACK = 5'b0_1000;
parameter [4:0] ST_STOP = 5'b1_0000;
// signals for bit_controller
reg [3:0] core_cmd;
reg core_txd;
wire core_ack, core_rxd;
// signals for shift register
reg [7:0] sr; //8bit shift register
reg shift, ld;
// signals for state machine
wire go;
reg [2:0] dcnt;
wire cnt_done;
//
// Module body
//
// hookup bit_controller
i2c_master_bit_ctrl bit_controller (
.clk ( clk ),
.nReset ( nReset ),
.ena ( ena ),
.clk_cnt ( clk_cnt ),
.cmd ( core_cmd ),
.cmd_ack ( core_ack ),
.busy ( i2c_busy ),
.al ( i2c_al ),
.din ( core_txd ),
.dout ( core_rxd ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen )
);
// generate go-signal
assign go = (read | write | stop) & ~cmd_ack;
// assign dout output to shift-register
assign dout = sr;
// generate shift register
always @(posedge clk or negedge nReset)
if (!nReset)
sr <= 8'h0;
else if (ld)
sr <= din;
else if (shift)
sr <= {sr[6:0], core_rxd};
// generate counter
always @(posedge clk or negedge nReset)
if (!nReset)
dcnt <= 3'h0;
else if (ld)
dcnt <= 3'h7;
else if (shift)
dcnt <= dcnt - 3'h1;
assign cnt_done = ~(|dcnt);
//
// state machine
//
reg [4:0] c_state;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
core_cmd <= `I2C_CMD_NOP;
core_txd <= 1'b0;
shift <= 1'b0;
ld <= 1'b0;
cmd_ack <= 1'b0;
c_state <= ST_IDLE;
ack_out <= 1'b0;
end
else if (i2c_al)
begin
core_cmd <= `I2C_CMD_NOP;
core_txd <= 1'b0;
shift <= 1'b0;
ld <= 1'b0;
cmd_ack <= 1'b0;
c_state <= ST_IDLE;
ack_out <= 1'b0;
end
else
begin
// initially reset all signals
core_txd <= sr[7];
shift <= 1'b0;
ld <= 1'b0;
cmd_ack <= 1'b0;
case (c_state)
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= ST_START;
core_cmd <= `I2C_CMD_START;
end
else if (read)
begin
c_state <= ST_READ;
core_cmd <= `I2C_CMD_READ;
end
else if (write)
begin
c_state <= ST_WRITE;
core_cmd <= `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= ST_STOP;
core_cmd <= `I2C_CMD_STOP;
end
ld <= 1'b1;
end
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= ST_READ;
core_cmd <= `I2C_CMD_READ;
end
else
begin
c_state <= ST_WRITE;
core_cmd <= `I2C_CMD_WRITE;
end
ld <= 1'b1;
end
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= ST_ACK;
core_cmd <= `I2C_CMD_READ;
end
else
begin
c_state <= ST_WRITE; // stay in same state
core_cmd <= `I2C_CMD_WRITE; // write next bit
shift <= 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= ST_ACK;
core_cmd <= `I2C_CMD_WRITE;
end
else
begin
c_state <= ST_READ; // stay in same state
core_cmd <= `I2C_CMD_READ; // read next bit
end
shift <= 1'b1;
core_txd <= ack_in;
end
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= ST_STOP;
core_cmd <= `I2C_CMD_STOP;
end
else
begin
c_state <= ST_IDLE;
core_cmd <= `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= 1'b1;
end
else
core_txd <= ack_in;
ST_STOP:
if (core_ack)
begin
c_state <= ST_IDLE;
core_cmd <= `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= 1'b1;
end
endcase
end
endmodule
rtl/ip/i2c_master_defines.v
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/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master controller defines ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_defines.v,v 1.3 2001-11-05 11:59:25 rherveille Exp $
//
// $Date: 2001-11-05 11:59:25 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// I2C registers wishbone addresses
// bitcontroller states
`define I2C_CMD_NOP 4'b0000
`define I2C_CMD_START 4'b0001
`define I2C_CMD_STOP 4'b0010
`define I2C_CMD_WRITE 4'b0100
`define I2C_CMD_READ 4'b1000
rtl/ip/i2c_slave.v
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/*******************************************************************
*
* Module: i2c_slave.v
* Project: Ravenna
* Author: mshalan (modified by Tim Edwards)
* Description: An i2c slave for i2c master testbench
*
**********************************************************************/
module i2c_slave(
inout scl, sda
);
parameter[7:0] SIDLE=8'h1, SADDR=8'h2, SACK1=8'h4, SDATA=8'h8, SACK2=8'h10;
reg scl_en, sda_en;
reg sda_o, scl_o;
wire sda_i, scl_i;
assign sda = sda_en ? sda_o : 1'bz;
assign scl = scl_en ? scl_o : 1'bz;
assign scl_i = scl;
assign sda_i = sda;
reg[4:0] cntr;
reg[7:0] state, addr, data;
reg[1:0] cfsm;
// Start Bit
always @ (negedge sda_i)
if(scl_i) begin
state <= SADDR;
addr <= 8'd0;
data <= 0;
cntr <= 0;
end
always @ (posedge scl_i)
if(state == SADDR) begin
addr <= {addr[6:0], sda_i};
end
else
if(state == SDATA) begin
data <= {data[6:0], sda_i};
end
always @ (posedge scl_i)
if((state== SADDR) || (state==SDATA)) cntr <= cntr + 1;
always @ (negedge scl_i)
if(cntr==8 )
sda_en <= 1;
else
sda_en <= 0;
always @ (negedge scl_i)
if(cntr==8) state = SDATA;
else if((state== SDATA) && (cntr==17)) begin
state<=SIDLE;
$display("i2c Slave has received 0x%X - Address: 0x%X", data, addr);
end
initial begin
scl_en = 0;
sda_en = 0;
sda_o = 0;
state <= SIDLE;
end
endmodule
rtl/ip/simple_spi_master.v
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//----------------------------------------------------------------------------
// Module: simple_spi_master
//
//----------------------------------------------------------------------------
// Copyright (C) 2019 efabless, inc.
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
//--------------------------------------------------------------------
//
// resetn: active low async reset
// clk: master clock (before prescaler)
// stream:
// 0 = apply/release CSB separately for each byte
// 1 = apply CSB until stream bit is cleared
// mlb:
// 0 = msb 1st
// 1 = lsb 1st
// invsck:
// 0 = normal SCK
// 1 = inverted SCK
// invcsb:
// 0 = normal CSB (active low)
// 1 = inverted CSB (active high)
// mode:
// 0 = read and change data on opposite SCK edges
// 1 = read and change data on the same SCK edge
// enable:
// 0 = disable the SPI master
// 1 = enable the SPI master
// irqena:
// 0 = disable interrupt
// 1 = enable interrupt
// prescaler: count (in master clock cycles) of 1/2 SCK cycle.
//
// reg_dat_we:
// 1 = data write enable
// reg_dat_re:
// 1 = data read enable
// reg_cfg_*: Signaling for read/write of configuration register
// reg_dat_*: Signaling for read/write of data register
//
// err_out: Indicates attempt to read/write before data ready
// (failure to wait for reg_dat_wait to clear)
//
// Between "mode" and "invsck", all four standard SPI modes are supported
//
//--------------------------------------------------------------------
module simple_spi_master(
input resetn,
input clk, // master clock (assume 100MHz)
input [1:0] reg_cfg_we,
input [31:0] reg_cfg_di,
output [31:0] reg_cfg_do,
input reg_dat_we,
input reg_dat_re,
input [31:0] reg_dat_di,
output [31:0] reg_dat_do,
output reg_dat_wait,
output irq_out,
output reg err_out,
input sdi, // SPI input
output csb, // SPI chip select
output sck, // SPI clock
output reg sdo, // SPI output
output sdoenb // enable SDO output (active low)
);
parameter IDLE = 2'b00;
parameter SENDL = 2'b01;
parameter SENDH = 2'b10;
parameter FINISH = 2'b11;
reg done;
reg hsck, icsb;
// reg sdo;
reg [1:0] state;
reg isck;
// reg err_out;
reg [7:0] treg, rreg, d_latched;
reg [2:0] nbit;
reg [7:0] prescaler;
reg [7:0] count;
reg invsck;
reg invcsb;
reg mlb;
reg irqena;
reg stream;
reg mode;
reg enable;
// wire sdoenb;
// wire csb;
// wire irq_out;
// wire sck;
// Define behavior for inverted SCK and inverted CSB
assign csb = (invcsb) ? ~icsb : icsb;
assign sck = (invsck) ? ~isck : isck;
// No bidirectional 3-pin mode defined, so SDO is enabled whenever CSB is low.
assign sdoenb = icsb;
assign irq_out = irqena & done;
// Read configuration and data registers
assign reg_cfg_do = {17'd0, irqena, enable, stream, mode, invsck, invcsb, mlb, prescaler};
assign reg_dat_wait = ~done;
assign reg_dat_do = done ? rreg : ~0;
// Write configuration register
always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) begin
prescaler <= 8'd2;
invcsb <= 1'b0;
invsck <= 1'b0;
mlb <= 1'b0;
enable <= 1'b0;
irqena <= 1'b0;
stream <= 1'b0;
mode <= 1'b0;
end else begin
if (reg_cfg_we[0]) prescaler <= reg_cfg_di[7:0];
if (reg_cfg_we[1]) begin
mlb <= reg_cfg_di[8];
invcsb <= reg_cfg_di[9];
invsck <= reg_cfg_di[10];
mode <= reg_cfg_di[11];
stream <= reg_cfg_di[12];
enable <= reg_cfg_di[13];
irqena <= reg_cfg_di[14];
end //reg_cfg_we[1]
end //resetn
end //always
// Watch for read and write enables on clk, not hsck, so as not to
// miss them.
reg w_latched, r_latched;
always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) begin
err_out <= 1'b0;
w_latched <= 1'b0;
r_latched <= 1'b0;
d_latched <= 8'd0;
end else begin
// Clear latches on SEND, otherwise latch when seen
if (state == SENDL || state == SENDH) begin
if (reg_dat_we == 1'b0) begin
w_latched <= 1'b0;
end
end else begin
if (reg_dat_we == 1'b1) begin
if (done == 1'b0 && w_latched == 1'b1) begin
err_out <= 1'b1;
end else begin
w_latched <= 1'b1;
d_latched <= reg_dat_di[7:0];
err_out <= 1'b0;
end
end
end
if (reg_dat_re == 1'b1) begin
if (r_latched == 1'b1) begin
r_latched <= 1'b0;
end else begin
err_out <= 1'b1; // byte not available
end
end else if (state == FINISH) begin
r_latched <= 1'b1;
end if (state == SENDL || state == SENDH) begin
if (r_latched == 1'b1) begin
err_out <= 1'b1; // last byte was never read
end else begin
r_latched <= 1'b0;
end
end
end
end
// State transition.
always @(posedge hsck or negedge resetn) begin
if (resetn == 1'b0) begin
state <= IDLE;
nbit <= 3'd0;
icsb <= 1'b1;
done <= 1'b1;
end else begin
if (state == IDLE) begin
if (w_latched == 1'b1) begin
state <= SENDL;
nbit <= 3'd0;
icsb <= 1'b0;
done <= 1'b0;
end else begin
icsb <= ~stream;
end
end else if (state == SENDL) begin
state <= SENDH;
end else if (state == SENDH) begin
nbit <= nbit + 1;
if (nbit == 3'd7) begin
state <= FINISH;
end else begin
state <= SENDL;
end
end else if (state == FINISH) begin
icsb <= ~stream;
done <= 1'b1;
state <= IDLE;
end
end
end
// Set up internal clock. The enable bit gates the internal clock
// to shut down the master SPI when disabled.
always @(posedge clk or negedge resetn) begin
if (resetn == 1'b0) begin
count <= 8'd0;
hsck <= 1'b0;
end else begin
if (enable == 1'b0) begin
count <= 8'd0;
end else begin
count <= count + 1;
if (count == prescaler) begin
hsck <= ~hsck;
count <= 8'd0;
end // count
end // enable
end // resetn
end // always
// sck is half the rate of hsck
always @(posedge hsck or negedge resetn) begin
if (resetn == 1'b0) begin
isck <= 1'b0;
end else begin
if (state == IDLE || state == FINISH)
isck <= 1'b0;
else
isck <= ~isck;
end // resetn
end // always
// Main procedure: read, write, shift data
always @(posedge hsck or negedge resetn) begin
if (resetn == 1'b0) begin
rreg <= 8'hff;
treg <= 8'hff;
sdo <= 1'b0;
end else begin
if (isck == 1'b0 && (state == SENDL || state == SENDH)) begin
if (mlb == 1'b1) begin
// LSB first, sdi@msb -> right shift
rreg <= {sdi, rreg[7:1]};
end else begin
// MSB first, sdi@lsb -> left shift
rreg <= {rreg[6:0], sdi};
end
end // read on ~isck
if (w_latched == 1'b1) begin
if (mlb == 1'b1) begin
treg <= {1'b1, d_latched[7:1]};
sdo <= d_latched[0];
end else begin
treg <= {d_latched[6:0], 1'b1};
sdo <= d_latched[7];
end // mlb
end else if ((mode ^ isck) == 1'b1) begin
if (mlb == 1'b1) begin
// LSB first, shift right
treg <= {1'b1, treg[7:1]};
sdo <= treg[0];
end else begin
// MSB first shift LEFT
treg <= {treg[6:0], 1'b1};
sdo <= treg[7];
end // mlb
end // write on mode ^ isck
end // resetn
end // always
endmodule