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feat: add tiny version retrosoc design

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maksyuki committed 2025-02-28 15:22:34 +08:00
1 parent 18e50b43f1
commit 1d38e5a94b
5 files changed
+1007 -1
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rtl/Makefile
+26 -1
View File
@@ -38,7 +38,9 @@ VTIME_OPTION := +notimingcheck \
# RTL code
WAVE := NONE
RTL_SOC := ./retrosoc_asic.v \
./retrosoc_asic_tiny.v \
./retrosoc.v \
./retrosoc_tiny.v \
./picorv32.v
RTL_IP := ./ip/spram_model.v \
@@ -84,7 +86,8 @@ RTL_IP := ./ip/spram_model.v \
./ip/cust/axil2apb/read_data_mux.v \
./ip/cust/axil2apb/apb_master.v \
./ip/cust/axil2apb/axi_apb_bridge.v \
./ip/axil_ip_wrapper.v
./ip/axil_ip_wrapper.v \
./ip/axil_ip_wrapper_tiny.v
RTL_TECH := ../tech/tc_io.v \
../tech/tc_clk.v \
@@ -148,6 +151,28 @@ retrosoc_syn_tb.vvp:
@mkdir -p build
(iverilog -DFUNCTIONAL $(RTL_INC) -s retrosoc_tb -o $@ retrosoc_tb.v ../syn/yosys/out/retrosoc_asic_yosys.v $(RTL_TECH) $(RTL_PDK) $(RTL_IP) || exit -1) 2>&1 | tee syncompile.log
# +behv_wave
retrosimtiny: retrosoc_tb_tiny.vvp $(FIRMWARE_NAME).elf
ln -sf $(FIRMWARE_NAME).hex mem_Q128_bottom.vmf
vvp -l run.log -N $< +behv_$(WAVE) +sim_$(SIM_TOOL) -fst
# +syn_wave
retrosynsimtiny: retrosoc_syn_tb_tiny.vvp $(FIRMWARE_NAME).elf
ln -sf $(FIRMWARE_NAME).hex mem_Q128_bottom.vmf
vvp -l synrun.log -N $< +syn_$(WAVE) +sim_$(SIM_TOOL) -fst
retrosoc_tb_tiny.vvp:
@mkdir -p build
(iverilog -DFUNCTIONAL $(RTL_INC) -s retrosoc_tb_tiny -o $@ retrosoc_tb_tiny.v $(RTL_SOC) $(RTL_TECH) $(RTL_PDK) $(RTL_IP) || exit -1) 2>&1 | tee compile.log
retrosoc_syn_tb_tiny.vvp:
@mkdir -p build
(iverilog -DFUNCTIONAL $(RTL_INC) -s retrosoc_tb_tiny -o $@ retrosoc_tb_tiny.v ../syn/yosys/out/retrosoc_asic_yosys.v $(RTL_TECH) $(RTL_PDK) $(RTL_IP) || exit -1) 2>&1 | tee syncompile.log
../syn/yosys/out/retrosoc_asic_yosys.v:
$(MAKE) -C ../syn/yosys -f yosys.mk
rtl/ip/axil_ip_wrapper_tiny.v
+169
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@@ -0,0 +1,169 @@
module axil_ip_wrapper_tiny (
input clk_i,
input rst_n_i,
input mem_axi_awvalid,
output mem_axi_awready,
input [31:0] mem_axi_awaddr,
input [ 2:0] mem_axi_awprot,
input mem_axi_wvalid,
output mem_axi_wready,
input [31:0] mem_axi_wdata,
input [ 3:0] mem_axi_wstrb,
output mem_axi_bvalid,
input mem_axi_bready,
input mem_axi_arvalid,
output mem_axi_arready,
input [31:0] mem_axi_araddr,
input [ 2:0] mem_axi_arprot,
output mem_axi_rvalid,
input mem_axi_rready,
output [31:0] mem_axi_rdata,
// qspi
output qspi_spi_clk_o,
output [ 3:0] qspi_spi_csn_o,
output [ 3:0] qspi_spi_sdo_o,
output [ 3:0] qspi_spi_oe_o,
input [ 3:0] qspi_spi_sdi_i,
output qspi_irq_o,
// spfs
input spfs_div4_i,
output spfs_clk_o,
output spfs_cs_o,
output spfs_mosi_o,
input spfs_miso_i,
output spfs_irq_o
);
localparam APB_SLAVES_NUM = 2;
localparam [32*APB_SLAVES_NUM-1 : 0] MEM_REGIONS1 = {32'h3000_0000, 32'h0300_7000};
localparam [32*APB_SLAVES_NUM-1 : 0] MEM_REGIONS2 = {32'h3FFF_FFFF, 32'h0300_7FFF};
wire [ 31:0] s_m_apb_paddr;
wire [ 2:0] s_m_apb_pprot;
wire [APB_SLAVES_NUM-1:0] s_m_apb_psel;
wire s_m_apb_penable;
wire s_m_apb_pwrite;
wire [ 31:0] s_m_apb_pwdata;
wire [ 3:0] s_m_apb_pstrb;
wire [APB_SLAVES_NUM-1:0] s_m_apb_pready;
wire [ 31:0] s_m_apb_prdata1;
wire [ 31:0] s_m_apb_prdata2;
wire [APB_SLAVES_NUM-1:0] s_m_apb_pslverr;
apb_spi_master #(
.BUFFER_DEPTH (4),
.APB_ADDR_WIDTH(32)
) u_apb_spi_master (
.HCLK (clk_i),
.HRESETn (rst_n_i),
.PADDR (s_m_apb_paddr),
.PWDATA (s_m_apb_pwdata),
.PWRITE (s_m_apb_pwrite),
.PSEL (s_m_apb_psel[0]),
.PENABLE (s_m_apb_penable),
.PRDATA (s_m_apb_prdata1),
.PREADY (s_m_apb_pready[0]),
.PSLVERR (s_m_apb_pslverr[0]),
.spi_clk (qspi_spi_clk_o),
.spi_csn0(qspi_spi_csn_o[0]),
.spi_csn1(qspi_spi_csn_o[1]),
.spi_csn2(qspi_spi_csn_o[2]),
.spi_csn3(qspi_spi_csn_o[3]),
.spi_sdo0(qspi_spi_sdo_o[0]),
.spi_sdo1(qspi_spi_sdo_o[1]),
.spi_sdo2(qspi_spi_sdo_o[2]),
.spi_sdo3(qspi_spi_sdo_o[3]),
.spi_oe0 (qspi_spi_oe_o[0]),
.spi_oe1 (qspi_spi_oe_o[1]),
.spi_oe2 (qspi_spi_oe_o[2]),
.spi_oe3 (qspi_spi_oe_o[3]),
.spi_sdi0(qspi_spi_sdi_i[0]),
.spi_sdi1(qspi_spi_sdi_i[1]),
.spi_sdi2(qspi_spi_sdi_i[2]),
.spi_sdi3(qspi_spi_sdi_i[3]),
.events_o(qspi_irq_o)
);
spi_flash #(
.flash_addr_start(32'h3000_0000),
.flash_addr_end (32'h3FFF_FFFF),
.spi_cs_num (1)
) u_spi_flash (
.pclk (clk_i),
.presetn (rst_n_i),
.paddr (s_m_apb_paddr),
.psel (s_m_apb_psel[1]),
.penable (s_m_apb_penable),
.pwrite (s_m_apb_pwrite),
.pwdata (s_m_apb_pwdata),
.pwstrb (4'hF),
.pready (s_m_apb_pready[1]),
.prdata (s_m_apb_prdata2),
.pslverr (s_m_apb_pslverr[1]),
.div4_i (spfs_div4_i),
.spi_clk (spfs_clk_o),
.spi_cs (spfs_cs_o),
.spi_mosi (spfs_mosi_o),
.spi_miso (spfs_miso_i),
.spi_irq_out(spfs_irq_o)
);
axi_apb_bridge #(
.c_apb_num_slaves(APB_SLAVES_NUM),
.memory_regions1 (MEM_REGIONS1),
.memory_regions2 (MEM_REGIONS2),
.timeout_val (32'hFFFF_FFFF),
.APB_Protocol (4)
) u_axi_apb_bridge (
.s_axi_clk (clk_i),
.s_axi_aresetn(rst_n_i),
.s_axi_awaddr (mem_axi_awaddr),
.s_axi_awvalid(mem_axi_awvalid),
.s_axi_awready(mem_axi_awready),
.s_axi_wdata (mem_axi_wdata),
.s_axi_wvalid (mem_axi_wvalid),
.s_axi_wstrb (mem_axi_wstrb),
.s_axi_wready (mem_axi_wready),
.s_axi_bresp (),
.s_axi_bvalid (mem_axi_bvalid),
.s_axi_bready (mem_axi_bready),
.s_axi_araddr (mem_axi_araddr),
.s_axi_arvalid(mem_axi_arvalid),
.s_axi_arready(mem_axi_arready),
.s_axi_rresp (),
.s_axi_rvalid (mem_axi_rvalid),
.s_axi_rdata (mem_axi_rdata),
.s_axi_rready (mem_axi_rready),
.s_axi_arprot (mem_axi_arprot),
.s_axi_awprot (mem_axi_awprot),
.m_apb_paddr (s_m_apb_paddr),
.m_apb_pprot (s_m_apb_pprot),
.m_apb_psel (s_m_apb_psel),
.m_apb_penable (s_m_apb_penable),
.m_apb_pwrite (s_m_apb_pwrite),
.m_apb_pwdata (s_m_apb_pwdata),
.m_apb_pstrb (s_m_apb_pstrb),
.m_apb_pready (s_m_apb_pready),
// diff apb slave rdata
.m_apb_prdata (s_m_apb_prdata1),
.m_apb_prdata2 (s_m_apb_prdata2),
.m_apb_prdata3 (32'h0),
.m_apb_prdata4 (32'h0),
.m_apb_prdata5 (32'h0),
.m_apb_prdata6 (32'h0),
.m_apb_prdata7 (32'h0),
.m_apb_prdata8 (32'h0),
.m_apb_prdata9 (32'h0),
.m_apb_prdata10(32'h0),
.m_apb_prdata11(32'h0),
.m_apb_prdata12(32'h0),
.m_apb_prdata13(32'h0),
.m_apb_prdata14(32'h0),
.m_apb_prdata15(32'h0),
.m_apb_prdata16(32'h0),
.m_apb_pslverr (s_m_apb_pslverr)
);
endmodule
rtl/retrosoc_asic_tiny.v
+186
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@@ -0,0 +1,186 @@
/*
* retrosoc_asic - A full example SoC using PicoRV32 in ASIC
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2018,2019 Tim Edwards <tim@efabless.com>
* Copyright (C) 2025 Yuchi Miao <miaoyuchi@ict.ac.cn>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`timescale 1 ns / 1 ps
// NOTE: need to focus on the port dir
module retrosoc_asic_tiny (
input extclk_i_pad,
input ext_rst_n_i_pad,
// UART
output uart_tx_o_pad,
input uart_rx_i_pad,
// GPIO
output gpio_0_io_pad,
output gpio_1_io_pad,
output gpio_2_io_pad,
output gpio_3_io_pad,
output gpio_4_io_pad,
output gpio_5_io_pad,
output gpio_6_io_pad,
output gpio_7_io_pad,
output gpio_8_io_pad,
output gpio_9_io_pad,
output gpio_10_io_pad,
output gpio_11_io_pad,
output gpio_12_io_pad,
output gpio_13_io_pad,
output gpio_14_io_pad,
output gpio_15_io_pad,
// CUST
output cust_qspi_spi_clk_o_pad,
output cust_qspi_spi_csn_0_o_pad,
output cust_qspi_spi_csn_1_o_pad,
output cust_qspi_spi_csn_2_o_pad,
output cust_qspi_spi_csn_3_o_pad,
inout cust_qspi_dat_0_io_pad,
inout cust_qspi_dat_1_io_pad,
inout cust_qspi_dat_2_io_pad,
inout cust_qspi_dat_3_io_pad,
output cust_psram_sclk_o_pad,
output cust_psram_ce_o_pad,
inout cust_psram_sio0_io_pad,
inout cust_psram_sio1_io_pad,
inout cust_psram_sio2_io_pad,
inout cust_psram_sio3_io_pad,
output cust_spfs_clk_o_pad,
output cust_spfs_cs_o_pad,
output cust_spfs_mosi_o_pad,
inout cust_spfs_miso_i_pad
);
// ip
wire s_ext_clk_i;
wire s_ext_rst_n_i;
wire s_uart_tx_o;
wire s_uart_rx_i;
wire [15:0] s_gpio_out_o;
wire [15:0] s_gpio_in_i;
wire [15:0] s_gpio_outenb_o;
wire [15:0] s_gpio_pullupb_o;
wire [15:0] s_gpio_pulldownb_o;
wire s_cust_qspi_spi_clk_o;
wire [ 3:0] s_cust_qspi_spi_csn_o;
wire [ 3:0] s_cust_qspi_spi_sdo_o;
wire [ 3:0] s_cust_qspi_spi_oe_o;
wire [ 3:0] s_cust_qspi_spi_sdi_i;
wire s_cust_psram_sclk_o;
wire s_cust_psram_ce_o;
wire s_cust_psram_sio0_i;
wire s_cust_psram_sio1_i;
wire s_cust_psram_sio2_i;
wire s_cust_psram_sio3_i;
wire s_cust_psram_sio0_o;
wire s_cust_psram_sio1_o;
wire s_cust_psram_sio2_o;
wire s_cust_psram_sio3_o;
wire s_cust_psram_sio_oe_o;
wire s_cust_spfs_clk_o;
wire s_cust_spfs_cs_o;
wire s_cust_spfs_mosi_o;
wire s_cust_spfs_miso_i;
// verilog_format: off
tc_io_tri_pad u_extclk_i_pad (.pad(extclk_i_pad), .c2p(), .c2p_en(1'b0), .p2c(s_ext_clk_i));
tc_io_tri_schmitt_pad u_ext_rst_n_i_pad (.pad(ext_rst_n_i_pad), .c2p(), .c2p_en(1'b0), .p2c(s_ext_rst_n_i));
tc_io_tri_pad u_uart_tx_o_pad (.pad(uart_tx_o_pad), .c2p(s_uart_tx_o), .c2p_en(1'b1), .p2c());
tc_io_tri_pad u_uart_rx_i_pad (.pad(uart_rx_i_pad), .c2p(), .c2p_en(1'b0), .p2c(s_uart_rx_i));
tc_io_tri_pad u_gpio_0_io_pad (.pad(gpio_0_io_pad), .c2p(s_gpio_out_o[0]), .c2p_en(~s_gpio_outenb_o[0]), .p2c(s_gpio_in_i[0]));
tc_io_tri_pad u_gpio_1_io_pad (.pad(gpio_1_io_pad), .c2p(s_gpio_out_o[1]), .c2p_en(~s_gpio_outenb_o[1]), .p2c(s_gpio_in_i[1]));
tc_io_tri_pad u_gpio_2_io_pad (.pad(gpio_2_io_pad), .c2p(s_gpio_out_o[2]), .c2p_en(~s_gpio_outenb_o[2]), .p2c(s_gpio_in_i[2]));
tc_io_tri_pad u_gpio_3_io_pad (.pad(gpio_3_io_pad), .c2p(s_gpio_out_o[3]), .c2p_en(~s_gpio_outenb_o[3]), .p2c(s_gpio_in_i[3]));
tc_io_tri_pad u_gpio_4_io_pad (.pad(gpio_4_io_pad), .c2p(s_gpio_out_o[4]), .c2p_en(~s_gpio_outenb_o[4]), .p2c(s_gpio_in_i[4]));
tc_io_tri_pad u_gpio_5_io_pad (.pad(gpio_5_io_pad), .c2p(s_gpio_out_o[5]), .c2p_en(~s_gpio_outenb_o[5]), .p2c(s_gpio_in_i[5]));
tc_io_tri_pad u_gpio_6_io_pad (.pad(gpio_6_io_pad), .c2p(s_gpio_out_o[6]), .c2p_en(~s_gpio_outenb_o[6]), .p2c(s_gpio_in_i[6]));
tc_io_tri_pad u_gpio_7_io_pad (.pad(gpio_7_io_pad), .c2p(s_gpio_out_o[7]), .c2p_en(~s_gpio_outenb_o[7]), .p2c(s_gpio_in_i[7]));
tc_io_tri_schmitt_pad u_gpio_8_io_pad (.pad(gpio_8_io_pad), .c2p(s_gpio_out_o[8]), .c2p_en(~s_gpio_outenb_o[8]), .p2c(s_gpio_in_i[8]));
tc_io_tri_schmitt_pad u_gpio_9_io_pad (.pad(gpio_9_io_pad), .c2p(s_gpio_out_o[9]), .c2p_en(~s_gpio_outenb_o[9]), .p2c(s_gpio_in_i[9]));
tc_io_tri_schmitt_pad u_gpio_10_io_pad (.pad(gpio_10_io_pad), .c2p(s_gpio_out_o[10]), .c2p_en(~s_gpio_outenb_o[10]), .p2c(s_gpio_in_i[10]));
tc_io_tri_schmitt_pad u_gpio_11_io_pad (.pad(gpio_11_io_pad), .c2p(s_gpio_out_o[11]), .c2p_en(~s_gpio_outenb_o[11]), .p2c(s_gpio_in_i[11]));
tc_io_tri_schmitt_pad u_gpio_12_io_pad (.pad(gpio_12_io_pad), .c2p(s_gpio_out_o[12]), .c2p_en(~s_gpio_outenb_o[12]), .p2c(s_gpio_in_i[12]));
tc_io_tri_schmitt_pad u_gpio_13_io_pad (.pad(gpio_13_io_pad), .c2p(s_gpio_out_o[13]), .c2p_en(~s_gpio_outenb_o[13]), .p2c(s_gpio_in_i[13]));
tc_io_tri_schmitt_pad u_gpio_14_io_pad (.pad(gpio_14_io_pad), .c2p(s_gpio_out_o[14]), .c2p_en(~s_gpio_outenb_o[14]), .p2c(s_gpio_in_i[14]));
tc_io_tri_schmitt_pad u_gpio_15_io_pad (.pad(gpio_15_io_pad), .c2p(s_gpio_out_o[15]), .c2p_en(~s_gpio_outenb_o[15]), .p2c(s_gpio_in_i[15]));
// cust
tc_io_tri_pad u_cust_qspi_spi_clk_o_pad (.pad(cust_qspi_spi_clk_o_pad), .c2p(s_cust_qspi_spi_clk_o), .c2p_en(1'b1), .p2c());
tc_io_tri_pad u_cust_qspi_spi_csn_0_o_pad(.pad(cust_qspi_spi_csn_0_o_pad), .c2p(s_cust_qspi_spi_csn_o[0]), .c2p_en(1'b1), .p2c());
tc_io_tri_pad u_cust_qspi_spi_csn_1_o_pad(.pad(cust_qspi_spi_csn_1_o_pad), .c2p(s_cust_qspi_spi_csn_o[1]), .c2p_en(1'b1), .p2c());
tc_io_tri_pad u_cust_qspi_spi_csn_2_o_pad(.pad(cust_qspi_spi_csn_2_o_pad), .c2p(s_cust_qspi_spi_csn_o[2]), .c2p_en(1'b1), .p2c());
tc_io_tri_pad u_cust_qspi_spi_csn_3_o_pad(.pad(cust_qspi_spi_csn_3_o_pad), .c2p(s_cust_qspi_spi_csn_o[3]), .c2p_en(1'b1), .p2c());
tc_io_tri_pad u_cust_qspi_dat_0_io_pad (.pad(cust_qspi_dat_0_io_pad), .c2p(s_cust_qspi_spi_sdo_o[0]), .c2p_en(s_cust_qspi_spi_oe_o[0]), .p2c(s_cust_qspi_spi_sdi_i[0]));
tc_io_tri_pad u_cust_qspi_dat_1_io_pad (.pad(cust_qspi_dat_1_io_pad), .c2p(s_cust_qspi_spi_sdo_o[1]), .c2p_en(s_cust_qspi_spi_oe_o[1]), .p2c(s_cust_qspi_spi_sdi_i[1]));
tc_io_tri_pad u_cust_qspi_dat_2_io_pad (.pad(cust_qspi_dat_2_io_pad), .c2p(s_cust_qspi_spi_sdo_o[2]), .c2p_en(s_cust_qspi_spi_oe_o[2]), .p2c(s_cust_qspi_spi_sdi_i[2]));
tc_io_tri_pad u_cust_qspi_dat_3_io_pad (.pad(cust_qspi_dat_3_io_pad), .c2p(s_cust_qspi_spi_sdo_o[3]), .c2p_en(s_cust_qspi_spi_oe_o[3]), .p2c(s_cust_qspi_spi_sdi_i[3]));
tc_io_tri_pad u_cust_psram_sclk_o_pad (.pad(cust_psram_sclk_o_pad), .c2p(s_cust_psram_sclk_o), .c2p_en(1'b1), .p2c());
tc_io_tri_pad u_cust_psram_ce_o_pad (.pad(cust_psram_ce_o_pad), .c2p(s_cust_psram_ce_o), .c2p_en(1'b1), .p2c());
tc_io_tri_pad u_cust_psram_sio0_io_pad (.pad(cust_psram_sio0_io_pad), .c2p(s_cust_psram_sio0_o), .c2p_en(~s_cust_psram_sio_oe_o), .p2c(s_cust_psram_sio0_i));
tc_io_tri_pad u_cust_psram_sio1_io_pad (.pad(cust_psram_sio1_io_pad), .c2p(s_cust_psram_sio1_o), .c2p_en(~s_cust_psram_sio_oe_o), .p2c(s_cust_psram_sio1_i));
tc_io_tri_pad u_cust_psram_sio2_io_pad (.pad(cust_psram_sio2_io_pad), .c2p(s_cust_psram_sio2_o), .c2p_en(~s_cust_psram_sio_oe_o), .p2c(s_cust_psram_sio2_i));
tc_io_tri_pad u_cust_psram_sio3_io_pad (.pad(cust_psram_sio3_io_pad), .c2p(s_cust_psram_sio3_o), .c2p_en(~s_cust_psram_sio_oe_o), .p2c(s_cust_psram_sio3_i));
tc_io_tri_pad u_cust_spfs_clk_o_pad (.pad(cust_spfs_clk_o_pad), .c2p(s_cust_spfs_clk_o), .c2p_en(1'b1), .p2c());
tc_io_tri_pad u_cust_spfs_cs_o_pad (.pad(cust_spfs_cs_o_pad), .c2p(s_cust_spfs_cs_o), .c2p_en(1'b1), .p2c());
tc_io_tri_pad u_cust_spfs_mosi_o_pad (.pad(cust_spfs_mosi_o_pad), .c2p(s_cust_spfs_mosi_o), .c2p_en(1'b1), .p2c());
tc_io_tri_pad u_cust_spfs_miso_i_pad (.pad(cust_spfs_miso_i_pad), .c2p(), .c2p_en(1'b0), .p2c(s_cust_spfs_miso_i));
// verilog_format: on
retrosoc_tiny u_retrosoc_tiny (
.clk_i (s_ext_clk_i),
.rst_n_i (s_ext_rst_n_i),
.clk_ext_sel_i (1'b1),
.gpio_out_o (s_gpio_out_o),
.gpio_in_i (s_gpio_in_i),
.gpio_pullupb_o (s_gpio_pullupb_o),
.gpio_pulldownb_o (s_gpio_pulldownb_o),
.gpio_outenb_o (s_gpio_outenb_o),
.spi_slv_ro_config_i (8'd0),
.spi_slv_ro_xtal_ena_i (1'b0),
.spi_slv_ro_reg_ena_i (1'b0),
.spi_slv_ro_pll_cp_ena_i (1'b0),
.spi_slv_ro_pll_vco_ena_i (1'b0),
.spi_slv_ro_pll_bias_ena_i(1'b0),
.spi_slv_ro_pll_trim_i (4'd0),
.spi_slv_ro_mfgr_id_i (12'd0),
.spi_slv_ro_prod_id_i (8'd0),
.spi_slv_ro_mask_rev_i (4'd0),
.uart_tx_o (s_uart_tx_o),
.uart_rx_i (s_uart_rx_i),
.cust_qspi_spi_clk_o (s_cust_qspi_spi_clk_o),
.cust_qspi_spi_csn_o (s_cust_qspi_spi_csn_o),
.cust_qspi_spi_sdo_o (s_cust_qspi_spi_sdo_o),
.cust_qspi_spi_oe_o (s_cust_qspi_spi_oe_o),
.cust_qspi_spi_sdi_i (s_cust_qspi_spi_sdi_i),
.cust_psram_sclk_o (s_cust_psram_sclk_o),
.cust_psram_ce_o (s_cust_psram_ce_o),
.cust_psram_sio0_i (s_cust_psram_sio0_i),
.cust_psram_sio1_i (s_cust_psram_sio1_i),
.cust_psram_sio2_i (s_cust_psram_sio2_i),
.cust_psram_sio3_i (s_cust_psram_sio3_i),
.cust_psram_sio0_o (s_cust_psram_sio0_o),
.cust_psram_sio1_o (s_cust_psram_sio1_o),
.cust_psram_sio2_o (s_cust_psram_sio2_o),
.cust_psram_sio3_o (s_cust_psram_sio3_o),
.cust_psram_sio_oe_o (s_cust_psram_sio_oe_o),
.cust_spfs_div4_i (1'b0),
.cust_spfs_clk_o (s_cust_spfs_clk_o),
.cust_spfs_cs_o (s_cust_spfs_cs_o),
.cust_spfs_mosi_o (s_cust_spfs_mosi_o),
.cust_spfs_miso_i (s_cust_spfs_miso_i)
);
endmodule
rtl/retrosoc_tb_tiny.v
+150
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/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`timescale 1 ns / 1 ps
module retrosoc_tb_tiny;
localparam real EXT_CPU_FREQ = 64.0;
reg r_ext_clk;
reg r_rst_n;
wire s_uart_rx;
wire s_cust_psram_sclk;
wire s_cust_psram_ce;
wire s_cust_psram_sio0;
wire s_cust_psram_sio1;
wire s_cust_psram_sio2;
wire s_cust_psram_sio3;
wire s_cust_spfs_clk_o;
wire s_cust_spfs_cs_o;
wire s_cust_spfs_mosi_o;
wire s_cust_spfs_miso_i;
always #(1000 / EXT_CPU_FREQ / 2) r_ext_clk = (r_ext_clk === 1'b0);
retrosoc_asic_tiny u_retrosoc_asic_tiny (
.extclk_i_pad (r_ext_clk),
.ext_rst_n_i_pad (r_rst_n),
.uart_tx_o_pad (s_uart_tx),
.uart_rx_i_pad (1'b0),
.gpio_0_io_pad (),
.gpio_1_io_pad (),
.gpio_2_io_pad (),
.gpio_3_io_pad (),
.gpio_4_io_pad (),
.gpio_5_io_pad (),
.gpio_6_io_pad (),
.gpio_7_io_pad (),
.gpio_8_io_pad (),
.gpio_9_io_pad (),
.gpio_10_io_pad (),
.gpio_11_io_pad (),
.gpio_12_io_pad (),
.gpio_13_io_pad (),
.gpio_14_io_pad (),
.gpio_15_io_pad (),
.cust_qspi_spi_clk_o_pad (),
.cust_qspi_spi_csn_0_o_pad(),
.cust_qspi_spi_csn_1_o_pad(),
.cust_qspi_spi_csn_2_o_pad(),
.cust_qspi_spi_csn_3_o_pad(),
.cust_qspi_dat_0_io_pad (),
.cust_qspi_dat_1_io_pad (),
.cust_qspi_dat_2_io_pad (),
.cust_qspi_dat_3_io_pad (),
.cust_psram_sclk_o_pad (s_cust_psram_sclk),
.cust_psram_ce_o_pad (s_cust_psram_ce),
.cust_psram_sio0_io_pad (s_cust_psram_sio0),
.cust_psram_sio1_io_pad (s_cust_psram_sio1),
.cust_psram_sio2_io_pad (s_cust_psram_sio2),
.cust_psram_sio3_io_pad (s_cust_psram_sio3),
.cust_spfs_clk_o_pad (s_cust_spfs_clk_o),
.cust_spfs_cs_o_pad (s_cust_spfs_cs_o),
.cust_spfs_mosi_o_pad (s_cust_spfs_mosi_o),
.cust_spfs_miso_i_pad (s_cust_spfs_miso_i)
);
N25Qxxx u_N25Qxxx (
.C_ (s_cust_spfs_clk_o),
.S (s_cust_spfs_cs_o),
.DQ0 (s_cust_spfs_mosi_o),
.DQ1 (s_cust_spfs_miso_i),
.HOLD_DQ3 (),
.Vpp_W_DQ2(),
.Vcc ('d3000)
);
rs232 u_rs232_0 (
.rs232_rx_i(s_uart_tx),
.rs232_tx_o(s_uart_rx)
);
psram_model u_psram_model (
.sck (s_cust_psram_sclk),
.dio ({s_cust_psram_sio3, s_cust_psram_sio2, s_cust_psram_sio1, s_cust_psram_sio0}),
.ce_n(s_cust_psram_ce)
);
initial begin
r_rst_n = 1;
#43;
r_rst_n = 0;
#170701;
r_rst_n = 1;
end
initial begin
if ($test$plusargs("behv_wave")) begin
$display("gen behv sim wave");
if ($test$plusargs("sim_iver")) begin
$dumpfile("retrosoc_tb_tiny.fst");
$dumpvars(0, retrosoc_tb_tiny);
end else begin
// $fsdbDumpfile("retrosoc_tb.fsdb");
// $fsdbDumpvars(0);
end
repeat (200) begin
repeat (5000) @(posedge r_ext_clk);
end
$finish;
end else if ($test$plusargs("syn_wave")) begin
$display("gen syn sim wave");
if ($test$plusargs("sim_iver")) begin
$display("gen retrosoc_syn_tb_tiny.fst");
$dumpfile("retrosoc_syn_tb_tiny.fst");
$dumpvars(0, retrosoc_tb_tiny);
end else begin
// $fsdbDumpfile("retrosoc_syn_tb.fsdb");
// $fsdbDumpvars(0);
end
repeat (10) begin
$display("hello");
repeat (100) @(posedge r_ext_clk);
end
$finish;
end
// repeat (1500) begin
// repeat (5000) @(posedge r_ext_clk);
// $display("+5000 cycles");
// end
// $finish;
end
endmodule
rtl/retrosoc_tiny.v
+476
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/*
* retroSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2018,2019 Tim Edwards <tim@efabless.com>
* Copyright (C) 2025 Yuchi Miao <miaoyuchi@ict.ac.cn>
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
/* Note: Synthesize register memory from flops */
/* Inefficient, but not terribly so */
/* Also note: To avoid having a hard macro in the place & route */
/* (method not finished yet in qflow), SRAM pins are brought out to */
/* the retrosoc I/O so that raven_soc.v itself is fully */
/* synthesizable and routable with qflow as-is. */
module retrosoc_tiny #(
parameter integer MEM_WORDS = 16384 * 2,
parameter [31:0] STACKADDR = (4 * MEM_WORDS), // end of memory
parameter [31:0] PROGADDR_RESET = 32'h3000_0000 // flash
) (
input clk_i,
input rst_n_i,
input clk_ext_sel_i,
// memory mapped I/O signals
output [15:0] gpio_out_o,
input [15:0] gpio_in_i,
output [15:0] gpio_pullupb_o,
output [15:0] gpio_pulldownb_o,
output [15:0] gpio_outenb_o,
input [ 7:0] spi_slv_ro_config_i,
input spi_slv_ro_xtal_ena_i,
input spi_slv_ro_reg_ena_i,
input spi_slv_ro_pll_cp_ena_i,
input spi_slv_ro_pll_vco_ena_i,
input spi_slv_ro_pll_bias_ena_i,
input [ 3:0] spi_slv_ro_pll_trim_i,
input [11:0] spi_slv_ro_mfgr_id_i,
input [ 7:0] spi_slv_ro_prod_id_i,
input [ 3:0] spi_slv_ro_mask_rev_i,
output uart_tx_o,
input uart_rx_i,
// cust
output cust_qspi_spi_clk_o,
output [ 3:0] cust_qspi_spi_csn_o,
output [ 3:0] cust_qspi_spi_sdo_o,
output [ 3:0] cust_qspi_spi_oe_o,
input [ 3:0] cust_qspi_spi_sdi_i,
output cust_psram_sclk_o,
output cust_psram_ce_o,
input cust_psram_sio0_i,
input cust_psram_sio1_i,
input cust_psram_sio2_i,
input cust_psram_sio3_i,
output cust_psram_sio0_o,
output cust_psram_sio1_o,
output cust_psram_sio2_o,
output cust_psram_sio3_o,
output cust_psram_sio_oe_o,
input cust_spfs_div4_i,
output cust_spfs_clk_o,
output cust_spfs_cs_o,
output cust_spfs_mosi_o,
input cust_spfs_miso_i
);
// core mem native if
wire s_mem_valid;
wire s_mem_instr;
wire s_mem_ready;
wire [31:0] s_mem_addr;
wire [31:0] s_mem_wdata;
wire [ 3:0] s_mem_wstrb;
wire [31:0] s_mem_rdata;
// mem map io if
wire s_iomem_valid;
reg r_iomem_ready;
wire [ 3:0] s_iomem_wstrb;
wire [31:0] s_iomem_addr;
wire [31:0] s_iomem_wdata;
reg [31:0] r_iomem_rdata;
wire s_aximem_ready;
wire [31:0] s_aximem_rdata;
// psram if
wire s_psram_valid;
wire s_psram_ready;
wire [ 3:0] s_psram_wstrb;
wire [31:0] s_psram_addr;
wire [31:0] s_psram_wdata;
wire [31:0] s_psram_rdata;
// mmio ctrl regs
reg [15:0] r_gpio;
reg [15:0] r_gpio_pu;
reg [15:0] r_gpio_pd;
reg [15:0] r_gpio_oeb;
// mmio axil if
wire s_mem_axi_awvalid;
wire s_mem_axi_awready;
wire [31:0] s_mem_axi_awaddr;
wire [ 2:0] s_mem_axi_awprot;
wire s_mem_axi_wvalid;
wire s_mem_axi_wready;
wire [31:0] s_mem_axi_wdata;
wire [ 3:0] s_mem_axi_wstrb;
wire s_mem_axi_bvalid;
wire s_mem_axi_bready;
wire s_mem_axi_arvalid;
wire s_mem_axi_arready;
wire [31:0] s_mem_axi_araddr;
wire [ 2:0] s_mem_axi_arprot;
wire s_mem_axi_rvalid;
wire s_mem_axi_rready;
wire [31:0] s_mem_axi_rdata;
// irq
wire [31:0] s_irq;
wire s_irq_stall = 0;
wire s_irq_uart;
wire s_irq_tim0;
wire s_cust_qspi_irq;
wire s_cust_spfs_irq;
// GPIO assignments
assign gpio_out_o[0] = r_gpio[0];
assign gpio_out_o[1] = r_gpio[1];
assign gpio_out_o[2] = r_gpio[2];
assign gpio_out_o[3] = r_gpio[3];
assign gpio_out_o[4] = r_gpio[4];
assign gpio_out_o[5] = r_gpio[5];
assign gpio_out_o[6] = r_gpio[6];
assign gpio_out_o[7] = r_gpio[7];
assign gpio_out_o[8] = r_gpio[8];
assign gpio_out_o[9] = r_gpio[9];
assign gpio_out_o[10] = r_gpio[10];
assign gpio_out_o[11] = r_gpio[11];
assign gpio_out_o[12] = r_gpio[12];
assign gpio_out_o[13] = r_gpio[13];
assign gpio_out_o[14] = r_gpio[14];
assign gpio_out_o[15] = r_gpio[15];
assign gpio_outenb_o[0] = ~rst_n_i | r_gpio_oeb[0];
assign gpio_outenb_o[1] = ~rst_n_i | r_gpio_oeb[1];
assign gpio_outenb_o[2] = ~rst_n_i | r_gpio_oeb[2];
assign gpio_outenb_o[3] = ~rst_n_i | r_gpio_oeb[3];
assign gpio_outenb_o[4] = ~rst_n_i | r_gpio_oeb[4];
assign gpio_outenb_o[5] = ~rst_n_i | r_gpio_oeb[5];
assign gpio_outenb_o[6] = ~rst_n_i | r_gpio_oeb[6];
assign gpio_outenb_o[7] = ~rst_n_i | r_gpio_oeb[7];
assign gpio_outenb_o[8] = ~rst_n_i | r_gpio_oeb[8];
assign gpio_outenb_o[9] = ~rst_n_i | r_gpio_oeb[9];
assign gpio_outenb_o[10] = ~rst_n_i | r_gpio_oeb[10];
assign gpio_outenb_o[11] = ~rst_n_i | r_gpio_oeb[11];
assign gpio_outenb_o[12] = ~rst_n_i | r_gpio_oeb[12];
assign gpio_outenb_o[13] = ~rst_n_i | r_gpio_oeb[13];
assign gpio_outenb_o[14] = ~rst_n_i | r_gpio_oeb[14];
assign gpio_outenb_o[15] = ~rst_n_i | r_gpio_oeb[15];
assign gpio_pullupb_o[0] = r_gpio_pu[0];
assign gpio_pullupb_o[1] = r_gpio_pu[1];
assign gpio_pullupb_o[2] = r_gpio_pu[2];
assign gpio_pullupb_o[3] = r_gpio_pu[3];
assign gpio_pullupb_o[4] = r_gpio_pu[4];
assign gpio_pullupb_o[5] = r_gpio_pu[5];
assign gpio_pullupb_o[6] = r_gpio_pu[6];
assign gpio_pullupb_o[7] = r_gpio_pu[7];
assign gpio_pullupb_o[8] = r_gpio_pu[8];
assign gpio_pullupb_o[9] = r_gpio_pu[9];
assign gpio_pullupb_o[10] = r_gpio_pu[10];
assign gpio_pullupb_o[11] = r_gpio_pu[11];
assign gpio_pullupb_o[12] = r_gpio_pu[12];
assign gpio_pullupb_o[13] = r_gpio_pu[13];
assign gpio_pullupb_o[14] = r_gpio_pu[14];
assign gpio_pullupb_o[15] = r_gpio_pu[15];
assign gpio_pulldownb_o[0] = r_gpio_pd[0];
assign gpio_pulldownb_o[1] = r_gpio_pd[1];
assign gpio_pulldownb_o[2] = r_gpio_pd[2];
assign gpio_pulldownb_o[3] = r_gpio_pd[3];
assign gpio_pulldownb_o[4] = r_gpio_pd[4];
assign gpio_pulldownb_o[5] = r_gpio_pd[5];
assign gpio_pulldownb_o[6] = r_gpio_pd[6];
assign gpio_pulldownb_o[7] = r_gpio_pd[7];
assign gpio_pulldownb_o[8] = r_gpio_pd[8];
assign gpio_pulldownb_o[9] = r_gpio_pd[9];
assign gpio_pulldownb_o[10] = r_gpio_pd[10];
assign gpio_pulldownb_o[11] = r_gpio_pd[11];
assign gpio_pulldownb_o[12] = r_gpio_pd[12];
assign gpio_pulldownb_o[13] = r_gpio_pd[13];
assign gpio_pulldownb_o[14] = r_gpio_pd[14];
assign gpio_pulldownb_o[15] = r_gpio_pd[15];
assign s_irq[2:0] = 3'd0;
assign s_irq[3] = s_irq_stall;
assign s_irq[4] = s_irq_uart;
assign s_irq[5] = 1'b0;
assign s_irq[6] = 1'b0;
assign s_irq[7] = s_irq_tim0;
assign s_irq[8] = s_cust_qspi_irq;
assign s_irq[9] = s_cust_spfs_irq;
assign s_irq[31:10] = 22'd0;
// memory mapped IP
// 16 x GPIO
// 1 x UART
// 1 x TIMER
// AXIL WRAPPER
// 1 x QSPI
// 1 x PSRAM(8MB)
// 1 x SPFS(HP)
picorv32 #(
.PROGADDR_RESET (PROGADDR_RESET),
.PROGADDR_IRQ (32'h0000_0000),
.STACKADDR (STACKADDR),
.BARREL_SHIFTER (1),
.COMPRESSED_ISA (0),
.ENABLE_MUL (0),
.ENABLE_FAST_MUL (0),
.ENABLE_DIV (0),
.ENABLE_IRQ (1),
.ENABLE_IRQ_QREGS(0)
) u_picorv32 (
.clk (clk_i),
.resetn (rst_n_i),
.mem_valid(s_mem_valid),
.mem_instr(s_mem_instr),
.mem_ready(s_mem_ready),
.mem_addr (s_mem_addr),
.mem_wdata(s_mem_wdata),
.mem_wstrb(s_mem_wstrb),
.mem_rdata(s_mem_rdata),
.irq (s_irq),
.trap ()
);
// mmio native perip
assign s_iomem_valid = s_mem_valid && (s_mem_addr[31:24] == 8'h03 || s_mem_addr >= 32'h3000_0000);
assign s_iomem_wstrb = s_mem_wstrb;
assign s_iomem_addr = s_mem_addr;
assign s_iomem_wdata = s_mem_wdata;
// uart
wire s_simpleuart_reg_div_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_0010);
wire s_simpleuart_reg_dat_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_0014);
wire [31:0] s_simpleuart_reg_div_dout;
wire [31:0] s_simpleuart_reg_dat_dout;
wire s_simpleuart_reg_dat_wait;
// tim0
wire s_tim0_reg_cfg_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_005c);
wire s_tim0_reg_val_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_0060);
wire s_tim0_reg_dat_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_0064);
wire [31:0] s_tim0_reg_cfg_dout;
wire [31:0] s_tim0_reg_val_dout;
wire [31:0] s_tim0_reg_dat_dout;
// psram
wire s_psram_cfg_wait_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_0080);
wire s_psram_cfg_chd_sel = s_iomem_valid && (s_iomem_addr == 32'h0300_0084);
reg [ 4:0] r_psram_cfg_wait_din;
wire [ 4:0] s_psram_cfg_wait_dout;
reg [ 2:0] r_psram_cfg_chd_din;
wire [ 2:0] s_psram_cfg_chd_dout;
simpleuart u_simpleuart (
.clk (clk_i),
.resetn (rst_n_i),
.ser_tx (uart_tx_o),
.ser_rx (uart_rx_i),
.reg_div_we (s_simpleuart_reg_div_sel ? s_iomem_wstrb : 4'b0000),
.reg_div_di (s_iomem_wdata),
.reg_div_do (s_simpleuart_reg_div_dout),
.reg_dat_we (s_simpleuart_reg_dat_sel ? s_iomem_wstrb[0] : 1'b0),
.reg_dat_re (s_simpleuart_reg_dat_sel && !s_iomem_wstrb),
.reg_dat_di (s_iomem_wdata),
.reg_dat_do (s_simpleuart_reg_dat_dout),
.reg_dat_wait(s_simpleuart_reg_dat_wait),
.irq_out (s_irq_uart)
);
counter_timer u_counter_timer0 (
.resetn (rst_n_i),
.clkin (clk_i),
.reg_val_we(s_tim0_reg_val_sel ? s_iomem_wstrb[3:0] : 4'h0),
.reg_val_di(s_iomem_wdata),
.reg_val_do(s_tim0_reg_val_dout),
.reg_cfg_we(s_tim0_reg_cfg_sel ? s_iomem_wstrb[0] : 1'b0),
.reg_cfg_di(s_iomem_wdata),
.reg_cfg_do(s_tim0_reg_cfg_dout),
.reg_dat_we(s_tim0_reg_dat_sel ? s_iomem_wstrb[3:0] : 4'h0),
.reg_dat_di(s_iomem_wdata),
.reg_dat_do(s_tim0_reg_dat_dout),
.irq_out (s_irq_tim0)
);
assign s_psram_addr = s_mem_addr;
assign s_psram_wdata = s_mem_wdata;
assign s_psram_wstrb = s_mem_wstrb;
assign s_psram_valid = s_mem_valid && (s_mem_addr[31:24] == 8'h04);
psram_top u_psram_top (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.cfg_wait_wr_en_i(s_psram_cfg_wait_sel ? s_iomem_wstrb[0] : 1'b0),
.cfg_wait_i (r_psram_cfg_wait_din),
.cfg_wait_o (s_psram_cfg_wait_dout),
.cfg_chd_wr_en_i (s_psram_cfg_chd_sel ? s_iomem_wstrb[0] : 1'b0),
.cfg_chd_i (r_psram_cfg_chd_din),
.cfg_chd_o (s_psram_cfg_chd_dout),
.mem_valid_i (s_psram_valid),
.mem_ready_o (s_psram_ready),
.mem_addr_i ({1'b0, s_psram_addr[22:0]}),
.mem_wdata_i (s_psram_wdata),
.mem_wstrb_i (s_psram_wstrb),
.mem_rdata_o (s_psram_rdata),
.psram_sclk_o (cust_psram_sclk_o),
.psram_ce_o (cust_psram_ce_o),
.psram_mosi_i (cust_psram_sio0_i),
.psram_miso_i (cust_psram_sio1_i),
.psram_sio2_i (cust_psram_sio2_i),
.psram_sio3_i (cust_psram_sio3_i),
.psram_mosi_o (cust_psram_sio0_o),
.psram_miso_o (cust_psram_sio1_o),
.psram_sio2_o (cust_psram_sio2_o),
.psram_sio3_o (cust_psram_sio3_o),
.psram_sio_oen_o (cust_psram_sio_oe_o)
);
wire s_aximem_range = (s_iomem_addr[31:8] >= 24'h0300_10 && s_iomem_addr[31:8] <= 24'h03FF_FF) || s_iomem_addr >= 32'h3000_0000;
picorv32_axi_adapter u_core2axi (
.clk (clk_i),
.resetn (rst_n_i),
.mem_axi_awvalid(s_mem_axi_awvalid),
.mem_axi_awready(s_mem_axi_awready),
.mem_axi_awaddr (s_mem_axi_awaddr),
.mem_axi_awprot (s_mem_axi_awprot),
.mem_axi_wvalid (s_mem_axi_wvalid),
.mem_axi_wready (s_mem_axi_wready),
.mem_axi_wdata (s_mem_axi_wdata),
.mem_axi_wstrb (s_mem_axi_wstrb),
.mem_axi_bvalid (s_mem_axi_bvalid),
.mem_axi_bready (s_mem_axi_bready),
.mem_axi_arvalid(s_mem_axi_arvalid),
.mem_axi_arready(s_mem_axi_arready),
.mem_axi_araddr (s_mem_axi_araddr),
.mem_axi_arprot (s_mem_axi_arprot),
.mem_axi_rvalid (s_mem_axi_rvalid),
.mem_axi_rready (s_mem_axi_rready),
.mem_axi_rdata (s_mem_axi_rdata),
.mem_valid (s_iomem_valid && s_aximem_range),
.mem_instr (s_mem_instr),
.mem_ready (s_aximem_ready),
.mem_addr (s_iomem_addr),
.mem_wdata (s_iomem_wdata),
.mem_wstrb (s_iomem_wstrb),
.mem_rdata (s_aximem_rdata)
);
axil_ip_wrapper_tiny u_axil_ip_wrapper_tiny (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.mem_axi_awvalid(s_mem_axi_awvalid),
.mem_axi_awready(s_mem_axi_awready),
.mem_axi_awaddr (s_mem_axi_awaddr),
.mem_axi_awprot (s_mem_axi_awprot),
.mem_axi_wvalid (s_mem_axi_wvalid),
.mem_axi_wready (s_mem_axi_wready),
.mem_axi_wdata (s_mem_axi_wdata),
.mem_axi_wstrb (s_mem_axi_wstrb),
.mem_axi_bvalid (s_mem_axi_bvalid),
.mem_axi_bready (s_mem_axi_bready),
.mem_axi_arvalid(s_mem_axi_arvalid),
.mem_axi_arready(s_mem_axi_arready),
.mem_axi_araddr (s_mem_axi_araddr),
.mem_axi_arprot (s_mem_axi_arprot),
.mem_axi_rvalid (s_mem_axi_rvalid),
.mem_axi_rready (s_mem_axi_rready),
.mem_axi_rdata (s_mem_axi_rdata),
.qspi_spi_clk_o (cust_qspi_spi_clk_o),
.qspi_spi_csn_o (cust_qspi_spi_csn_o),
.qspi_spi_sdo_o (cust_qspi_spi_sdo_o),
.qspi_spi_oe_o (cust_qspi_spi_oe_o),
.qspi_spi_sdi_i (cust_qspi_spi_sdi_i),
.qspi_irq_o (s_cust_qspi_irq),
.spfs_div4_i (cust_spfs_div4_i),
.spfs_clk_o (cust_spfs_clk_o),
.spfs_cs_o (cust_spfs_cs_o),
.spfs_mosi_o (cust_spfs_mosi_o),
.spfs_miso_i (cust_spfs_miso_i),
.spfs_irq_o (s_cust_spfs_irq)
);
always @(posedge clk_i, negedge rst_n_i) begin
if (!rst_n_i) begin
r_gpio <= 0;
r_gpio_oeb <= 16'hffff;
r_gpio_pu <= 0;
r_gpio_pd <= 0;
end else begin
if (s_iomem_valid && !r_iomem_ready && s_iomem_addr[31:8] == 24'h0300_00) begin
// Handle r_iomem_ready based on wait states
case (s_iomem_addr[7:0])
8'h14: r_iomem_ready <= ~s_simpleuart_reg_dat_wait;
default: r_iomem_ready <= 1'b1;
endcase
case (s_iomem_addr[7:0])
8'h00: begin
r_iomem_rdata <= {gpio_out_o, gpio_in_i};
if (s_iomem_wstrb[0]) r_gpio[7:0] <= s_iomem_wdata[7:0];
if (s_iomem_wstrb[1]) r_gpio[15:8] <= s_iomem_wdata[15:8];
end
8'h04: begin
r_iomem_rdata <= {16'd0, r_gpio_oeb};
if (s_iomem_wstrb[0]) r_gpio_oeb[7:0] <= s_iomem_wdata[7:0];
if (s_iomem_wstrb[1]) r_gpio_oeb[15:8] <= s_iomem_wdata[15:8];
end
8'h08: begin
r_iomem_rdata <= {16'd0, r_gpio_pu};
if (s_iomem_wstrb[0]) r_gpio_pu[7:0] <= s_iomem_wdata[7:0];
if (s_iomem_wstrb[1]) r_gpio_pu[15:8] <= s_iomem_wdata[15:8];
end
8'h0c: begin
r_iomem_rdata <= {16'd0, r_gpio_pu};
if (s_iomem_wstrb[0]) r_gpio_pd[7:0] <= s_iomem_wdata[7:0];
if (s_iomem_wstrb[1]) r_gpio_pd[15:8] <= s_iomem_wdata[15:8];
end
8'h10: r_iomem_rdata <= s_simpleuart_reg_div_dout;
8'h14: r_iomem_rdata <= s_simpleuart_reg_dat_dout;
8'h18: r_iomem_rdata <= {24'd0, spi_slv_ro_config_i};
8'h1c: r_iomem_rdata <= {30'd0, spi_slv_ro_xtal_ena_i, spi_slv_ro_reg_ena_i};
8'h20: begin
r_iomem_rdata <= {
25'd0,
spi_slv_ro_pll_trim_i,
spi_slv_ro_pll_cp_ena_i,
spi_slv_ro_pll_vco_ena_i,
spi_slv_ro_pll_bias_ena_i
};
end
8'h24: r_iomem_rdata <= {20'd0, spi_slv_ro_mfgr_id_i};
8'h28: r_iomem_rdata <= {24'd0, spi_slv_ro_prod_id_i};
8'h2c: r_iomem_rdata <= {28'd0, spi_slv_ro_mask_rev_i};
8'h30: r_iomem_rdata <= {31'd0, clk_ext_sel_i};
8'h5c: r_iomem_rdata <= s_tim0_reg_cfg_dout;
8'h60: r_iomem_rdata <= s_tim0_reg_val_dout;
8'h64: r_iomem_rdata <= s_tim0_reg_dat_dout;
8'h80: begin
r_iomem_rdata <= {27'd0, s_psram_cfg_wait_dout};
if (s_iomem_wstrb[0]) r_psram_cfg_wait_din <= s_iomem_wdata[4:0];
end
8'h84: begin
r_iomem_rdata <= {29'd0, s_psram_cfg_chd_dout};
if (s_iomem_wstrb[0]) r_psram_cfg_chd_din <= s_iomem_wdata[2:0];
end
endcase
end else if (s_iomem_valid && !r_iomem_ready && s_aximem_range) begin
r_iomem_ready <= s_aximem_ready;
r_iomem_rdata <= s_aximem_rdata;
end else begin
r_iomem_ready <= 1'b0;
end
end
end
// data mux
assign s_mem_ready = (s_iomem_valid && r_iomem_ready) || s_psram_ready;
assign s_mem_rdata = (s_iomem_valid && r_iomem_ready) ? r_iomem_rdata :
s_psram_ready ? s_psram_rdata : 32'h0000_0000;
endmodule