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https://github.com/retroSoC/retroSoC.git
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feat: modify io and ram impl
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4 files changed
+75
-66
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+6
-3
@@ -12,12 +12,15 @@ retrosim: retrosoc_tb.vvp retrosoc_fw.hex retrosoc_fw.bin
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retrosynsim: retrosoc_syn_tb.vvp retrosoc_fw.hex
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vvp -N $< +firmware=retrosoc_fw.hex +syn_$(WAVE)
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retrosoc_tb.vvp: retrosoc_tb.v retrosoc.v spram_model.v spimemio.v simpleuart.v picosoc.v picorv32.v spiflash.v
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retrosoc_tb.vvp: retrosoc_tb.v retrosoc.v spram_model.v spimemio.v simpleuart.v picosoc.v picorv32.v spiflash.v ../tech/tc_io.v ../tech/tc_clk.v ../tech/tc_sram.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x16_c2_bm_bist.v
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iverilog -s retrosoc_tb -o $@ $^
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retrosoc_syn_tb.vvp: retrosoc_tb.v retrosoc_syn.v spiflash.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v
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retrosoc_syn_tb.vvp: retrosoc_tb.v ../syn/yosys/out/retrosoc_yosys.v spiflash.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_core_behavioral_bm_bist.v ../syn/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/verilog/RM_IHPSG13_1P_1024x16_c2_bm_bist.v
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iverilog -s retrosoc_tb -o $@ $^
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../syn/yosys/out/retrosoc_yosys.v:
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$(MAKE) -C ../syn/yosys -f yosys.mk
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retrosoc_syn.v:
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yosys ../syn/synth_retrosoc.ys
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@@ -52,4 +55,4 @@ clean:
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rm -f retrosoc_syn.v
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.PHONY: spiflash_tb clean
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.PHONY: retrosim retrosynsim retrosoc_syn.v
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.PHONY: retrosim retrosynsim retrosoc_syn.v
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+38
-36
@@ -31,23 +31,25 @@ module retrosoc #(
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) (
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input clk_i,
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input rst_n_i,
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output uart_tx_o,
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input uart_rx_i,
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output led1_o,
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output led2_o,
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output led3_o,
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output led4_o,
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output led5_o,
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output led6_o,
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output led7_o,
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output flash_csb_o,
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output flash_clk_o,
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inout flash_io0_io,
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inout flash_io1_io,
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inout flash_io2_io,
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inout flash_io3_io
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output uart_tx_o_pad,
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input uart_rx_i_pad,
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output flash_csb_o_pad,
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output flash_clk_o_pad,
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inout flash_io0_io_pad,
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inout flash_io1_io_pad,
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inout flash_io2_io_pad,
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inout flash_io3_io_pad,
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output led1_o_pad,
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output led2_o_pad,
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output led3_o_pad,
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output led4_o_pad,
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output led5_o_pad,
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output led6_o_pad,
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output led7_o_pad
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);
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wire s_flash_csb_o, s_flash_clk_o;
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wire s_uart_rx_i, s_uart_tx_o;
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wire s_flash_io0_oe, s_flash_io0_do, s_flash_io0_di;
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wire s_flash_io1_oe, s_flash_io1_do, s_flash_io1_di;
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wire s_flash_io2_oe, s_flash_io2_do, s_flash_io2_di;
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@@ -61,23 +63,23 @@ module retrosoc #(
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wire [ 7:0] s_leds;
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reg [31:0] r_gpio;
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assign flash_io0_io = s_flash_io0_oe ? s_flash_io0_do : 1'bz;
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assign s_flash_io0_di = flash_io0_io;
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assign flash_io1_io = s_flash_io1_oe ? s_flash_io1_do : 1'bz;
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assign s_flash_io1_di = flash_io1_io;
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assign flash_io2_io = s_flash_io2_oe ? s_flash_io2_do : 1'bz;
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assign s_flash_io2_di = flash_io2_io;
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assign flash_io3_io = s_flash_io3_oe ? s_flash_io3_do : 1'bz;
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assign s_flash_io3_di = flash_io3_io;
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assign led1_o = s_leds[1];
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assign led2_o = s_leds[2];
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assign led3_o = s_leds[3];
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assign led4_o = s_leds[4];
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assign led5_o = s_leds[5];
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assign led6_o = s_leds[6];
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assign led7_o = s_leds[7];
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assign s_leds = r_gpio;
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// verilog_format: off
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tc_io_tri_pad u_uart_tx_o_pad (.pad(uart_tx_o_pad), .c2p(s_uart_tx_o), .c2p_en(1'b1), .p2c());
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tc_io_tri_pad u_uart_rx_i_pad (.pad(uart_rx_i_pad), .c2p(), .c2p_en(1'b0), .p2c(s_uart_rx_i));
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tc_io_tri_pad u_flash_csb_o_pad (.pad(flash_csb_o_pad), .c2p(s_flash_csb_o), .c2p_en(1'b1), .p2c());
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tc_io_tri_pad u_flash_clk_o_pad (.pad(flash_clk_o_pad), .c2p(s_flash_clk_o), .c2p_en(1'b1), .p2c());
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tc_io_tri_pad u_flash_io0_io_pad(.pad(flash_io0_io_pad), .c2p(s_flash_io0_do), .c2p_en(s_flash_io0_oe), .p2c(s_flash_io0_di));
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tc_io_tri_pad u_flash_io1_io_pad(.pad(flash_io1_io_pad), .c2p(s_flash_io1_do), .c2p_en(s_flash_io1_oe), .p2c(s_flash_io1_di));
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tc_io_tri_pad u_flash_io2_io_pad(.pad(flash_io2_io_pad), .c2p(s_flash_io2_do), .c2p_en(s_flash_io2_oe), .p2c(s_flash_io2_di));
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tc_io_tri_pad u_led1_o_pad (.pad(led1_o_pad), .c2p(s_leds[1]), .c2p_en(1'b1), .p2c());
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tc_io_tri_pad u_led2_o_pad (.pad(led2_o_pad), .c2p(s_leds[2]), .c2p_en(1'b1), .p2c());
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tc_io_tri_pad u_led3_o_pad (.pad(led3_o_pad), .c2p(s_leds[3]), .c2p_en(1'b1), .p2c());
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tc_io_tri_pad u_led4_o_pad (.pad(led4_o_pad), .c2p(s_leds[4]), .c2p_en(1'b1), .p2c());
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tc_io_tri_pad u_led5_o_pad (.pad(led5_o_pad), .c2p(s_leds[5]), .c2p_en(1'b1), .p2c());
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tc_io_tri_pad u_led6_o_pad (.pad(led6_o_pad), .c2p(s_leds[6]), .c2p_en(1'b1), .p2c());
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tc_io_tri_pad u_led7_o_pad (.pad(led7_o_pad), .c2p(s_leds[7]), .c2p_en(1'b1), .p2c());
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// verilog_format: on
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assign s_leds = r_gpio;
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always @(posedge clk_i) begin
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if (!rst_n_i) begin
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@@ -104,10 +106,10 @@ module retrosoc #(
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) u_picosoc (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.uart_tx_o (uart_tx_o),
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.uart_rx_i (uart_rx_i),
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.flash_csb_o (flash_csb_o),
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.flash_clk_o (flash_clk_o),
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.uart_tx_o (s_uart_tx_o),
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.uart_rx_i (s_uart_rx_i),
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.flash_csb_o (s_flash_csb_o),
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.flash_clk_o (s_flash_clk_o),
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.flash_io0_oe_o(s_flash_io0_oe),
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.flash_io1_oe_o(s_flash_io1_oe),
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.flash_io2_oe_o(s_flash_io2_oe),
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+23
-23
@@ -50,23 +50,23 @@ module retrosoc_tb;
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end
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retrosoc u_retrosoc (
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.clk_i (r_clk),
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.rst_n_i (s_rst_n),
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.led1_o (s_led1),
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.led2_o (s_led2),
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.led3_o (s_led3),
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.led4_o (s_led4),
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.led5_o (s_led5),
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.led6_o (s_led6),
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.led7_o (s_led7),
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.uart_rx_i (s_uart_rx),
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.uart_tx_o (s_uart_tx),
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.flash_csb_o (s_flash_csb),
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.flash_clk_o (s_flash_clk),
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.flash_io0_io(s_flash_io0),
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.flash_io1_io(s_flash_io1),
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.flash_io2_io(s_flash_io2),
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.flash_io3_io(s_flash_io3)
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.clk_i (r_clk),
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.rst_n_i (s_rst_n),
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.uart_tx_o_pad (s_uart_tx),
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.uart_rx_i_pad (s_uart_rx),
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.flash_csb_o_pad (s_flash_csb),
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.flash_clk_o_pad (s_flash_clk),
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.flash_io0_io_pad(s_flash_io0),
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.flash_io1_io_pad(s_flash_io1),
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.flash_io2_io_pad(s_flash_io2),
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.flash_io3_io_pad(s_flash_io3),
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.led1_o_pad (s_led1),
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.led2_o_pad (s_led2),
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.led3_o_pad (s_led3),
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.led4_o_pad (s_led4),
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.led5_o_pad (s_led5),
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.led6_o_pad (s_led6),
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.led7_o_pad (s_led7)
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);
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spiflash u_spiflash (
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@@ -109,18 +109,18 @@ module retrosoc_tb;
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end
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initial begin
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if($test$plusargs("behv_wave")) begin
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if ($test$plusargs("behv_wave")) begin
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$dumpfile("retrosoc_tb.vcd");
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$dumpvars(0, retrosoc_tb);
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end else if($test$plusargs("syn_wave")) begin
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end else if ($test$plusargs("syn_wave")) begin
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$dumpfile("retrosoc_syn_tb.vcd");
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$dumpvars(0, retrosoc_tb);
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$dumpvars(0, retrosoc_tb);
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end
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repeat (100) begin
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repeat (5000) @(posedge r_clk);
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// $display("+5000 cycles");
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repeat (5000) @(posedge r_clk);
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// $display("+5000 cycles");
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end
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$finish;
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// $finish;
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end
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endmodule
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+8
-4
@@ -39,7 +39,8 @@ module spram_model (
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({32{cs_10}} & rdata_10) | ({32{cs_11}} & rdata_11);
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// 4x4KB=16KB
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SPRAM1024X32 u_ram00 (
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// SPRAM1024X32 u_ram00 (
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tc_sram_1024x32 u_ram00 (
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.clk_i (clk),
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.cs_i (cs_00),
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.addr_i(addr[9:0]),
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@@ -49,7 +50,8 @@ module spram_model (
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.data_o(rdata_00)
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);
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SPRAM1024X32 u_ram01 (
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// SPRAM1024X32 u_ram01 (
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tc_sram_1024x32 u_ram01 (
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.clk_i (clk),
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.cs_i (cs_01),
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.addr_i(addr[9:0]),
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@@ -59,7 +61,8 @@ module spram_model (
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.data_o(rdata_01)
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);
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SPRAM1024X32 u_ram10 (
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// SPRAM1024X32 u_ram10 (
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tc_sram_1024x32 u_ram10 (
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.clk_i (clk),
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.cs_i (cs_10),
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.addr_i(addr[9:0]),
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@@ -69,7 +72,8 @@ module spram_model (
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.data_o(rdata_10)
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);
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SPRAM1024X32 u_ram11 (
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// SPRAM1024X32 u_ram11 (
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tc_sram_1024x32 u_ram11 (
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.clk_i (clk),
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.cs_i (cs_11),
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.addr_i(addr[9:0]),
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