feat: add tech cell modules

tech/tc_clk.v

@@ -0,0 +1,84 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+// Authors:
+//
+// -Thomas Benz <tbenz@iis.ee.ethz.ch>
+// -Tobias Senti <tsenti@student.ethz.ch>
+module tc_clk_inverter (
+    input  clk_i,
+    output clk_o
+);
+
+  (* keep *) (* dont_touch = "true" *)
+  sg13g2_inv_1 i_inv (
+      .A(clk_i),
+      .Y(clk_o)
+  );
+
+endmodule
+
+module tc_clk_buffer (
+    input  clk_i,
+    output clk_o
+);
+
+  (* keep *) (* dont_touch = "true" *)
+  sg13g2_buf_1 i_buf (
+      .A(clk_i),
+      .X(clk_o)
+  );
+
+endmodule
+
+module tc_clk_mux2 (
+    input  clk0_i,
+    input  clk1_i,
+    input  clk_sel_i,
+    output clk_o
+);
+  (* keep *) (* dont_touch = "true" *)
+  sg13g2_mux2_1 i_mux (
+      .A0(clk0_i),
+      .A1(clk1_i),
+      .S (clk_sel_i),
+      .X (clk_o)
+  );
+endmodule
+
+module tc_clk_xor2 (
+    input  clk0_i,
+    input  clk1_i,
+    output clk_o
+);
+
+  (* keep *) (* dont_touch = "true" *)
+  sg13g2_xor2_1 i_mux (
+      .A(clk0_i),
+      .B(clk1_i),
+      .X(clk_o)
+  );
+endmodule
+
+module tc_clk_gating #(
+    parameter [0:0] IS_FUNCTIONAL = 1'b1
+) (
+    input  clk_i,
+    input  en_i,
+    input  test_en_i,
+    output clk_o
+);
+
+  //   if (IS_FUNCTIONAL || `ifdef USE_CLKGATE 1 `else 0 `endif) begin
+  //     (* keep *)(* dont_touch = "true" *)
+  //     sg13g2_slgcp_1 i_clkgate (
+  //       .GATE ( en_i  ),
+  //       .SCE  ( test_en_i ),
+  //       .CLK  ( clk_i ),
+  //       .GCLK ( clk_o )
+  //     );
+  //   end else begin
+  assign clk_o = clk_i;
+  //   end
+
+endmodule

tech/tc_io.v

@@ -0,0 +1,16 @@
+module tc_io_tri_pad (
+    inout  pad,
+    input  c2p,
+    input  c2p_en,
+    output p2c
+);
+
+  (* keep *) (* dont_touch = "true" *)
+  sg13g2_IOPadInOut4mA u_sg13g2_IOPadInOut4mA (
+      .pad   (pad),
+      .c2p   (c2p),
+      .c2p_en(c2p_en),
+      .p2c   (p2c)
+  );
+
+endmodule

tech/tc_sram.v

@@ -0,0 +1,53 @@
+module tc_sram_1024x32 (
+    input             clk_i,
+    input             cs_i,
+    input      [ 9:0] addr_i,
+    input      [31:0] data_i,
+    input      [ 3:0] mask_i,
+    input             wren_i,
+    output reg [31:0] data_o
+);
+
+  wire [15:0] s_rd_data_mem1, s_rd_data_mem2;
+  assign data_o = {s_rd_data_mem2, s_rd_data_mem1};
+
+  RM_IHPSG13_1P_1024x16_c2_bm_bist u_mem1 (
+      .A_CLK      (clk_i),
+      .A_ADDR     (addr_i[9:0]),
+      .A_BM       ({{8{mask_i[1]}}, {8{mask_i[0]}}}),
+      .A_MEN      (cs_i),
+      .A_WEN      (wren_i),
+      .A_REN      (~wren_i),
+      .A_DIN      (data_i[15:0]),
+      .A_DOUT     (s_rd_data_mem1),
+      .A_BIST_CLK (1'b0),
+      .A_BIST_ADDR(10'd0),
+      .A_BIST_DIN (16'd0),
+      .A_BIST_BM  (16'd0),
+      .A_BIST_MEN (1'b0),
+      .A_BIST_WEN (1'b0),
+      .A_BIST_REN (1'b0),
+      .A_BIST_EN  (1'b0),
+      .A_DLY      (1'b0)
+  );
+
+  RM_IHPSG13_1P_1024x16_c2_bm_bist u_mem2 (
+      .A_CLK      (clk_i),
+      .A_ADDR     (addr_i[9:0]),
+      .A_BM       ({{8{mask_i[3]}}, {8{mask_i[2]}}}),
+      .A_MEN      (cs_i),
+      .A_WEN      (wren_i),
+      .A_REN      (~wren_i),
+      .A_DIN      (data_i[31:16]),
+      .A_DOUT     (s_rd_data_mem2),
+      .A_BIST_CLK (1'b0),
+      .A_BIST_ADDR(10'd0),
+      .A_BIST_DIN (16'd0),
+      .A_BIST_BM  (16'd0),
+      .A_BIST_MEN (1'b0),
+      .A_BIST_WEN (1'b0),
+      .A_BIST_REN (1'b0),
+      .A_BIST_EN  (1'b0),
+      .A_DLY      (1'b0)
+  );
+endmodule