refactor: refactor RTL source paths in style audit and test files

- Added i2c_if.sv and spi_if.sv to rtl_style_audit.json for proper inclusion in style checks.
- Updated test_i2c.py to reference i2c_if.sv from the serial directory instead of the cluster IP directory.
- Modified test_spisd.py to point to spi_if.sv in the storage directory instead of the cluster IP directory.

.github/workflows/_regression.yml

@@ -65,17 +65,12 @@ jobs:
             physical/pdk/icsprout55-pdk
             physical/pdk/skywater-pdk
             rtl/managed/clusterip/archinfo
-            rtl/managed/clusterip/clint
             rtl/managed/clusterip/common
             rtl/managed/clusterip/crc
-            rtl/managed/clusterip/i2c
-            rtl/managed/clusterip/i2s
-            rtl/managed/clusterip/plic
             rtl/managed/clusterip/ps2
             rtl/managed/clusterip/pwm
             rtl/managed/clusterip/rng
             rtl/managed/clusterip/rtc
-            rtl/managed/clusterip/spi
             rtl/managed/clusterip/wdg
             rtl/managed/third_party
             rtl/managed/mpw

.github/workflows/release.yml

@@ -24,17 +24,12 @@ jobs:
             app/fatfs/ff16
             physical/pdk/IHP-Open-PDK
             rtl/managed/clusterip/archinfo
-            rtl/managed/clusterip/clint
             rtl/managed/clusterip/common
             rtl/managed/clusterip/crc
-            rtl/managed/clusterip/i2c
-            rtl/managed/clusterip/i2s
-            rtl/managed/clusterip/plic
             rtl/managed/clusterip/ps2
             rtl/managed/clusterip/pwm
             rtl/managed/clusterip/rng
             rtl/managed/clusterip/rtc
-            rtl/managed/clusterip/spi
             rtl/managed/clusterip/wdg
             rtl/managed/third_party
             rtl/managed/mpw

ATTRIBUTIONS.md

@@ -38,6 +38,15 @@ Several SPI SD card related RTL files retain the original attribution to EmbedFi
 
 These headers state that the original code was published on GitHub by EmbedFire, but that the original license was not specified in the retained header.
 
-## 5. Notes on redistribution
+## 5. Device simulation models
+
+The simulation-only models under `rtl/model/` retain their upstream notices
+and source formatting. The AT24 model is imported from the retroSoC I2C
+repository, the microphone model from the retroSoC I2S repository, and the
+W25Q128JVxIM model from the retroSoC SPI repository. The Winbond model retains
+its original Winbond Electronics Corporation copyright and "All Rights
+Reserved" notice; its inclusion does not relicense it under Mulan PSL v2.
+
+## 6. Notes on redistribution
 
 The preserved third-party notices are included to maintain attribution for code that was adapted or reused in this repository. They do not replace the repository's main license declaration. The retroSoC project itself is distributed under the Mulan PSL v2 license.

NOTICE

@@ -8,5 +8,8 @@ The following third-party projects or authors are referenced in the RTL source h
 - Ravenna / PicoRV32 in ASIC: notices are preserved in rtl/ip/peripheral/gpio.sv, rtl/ip/peripheral/timer.sv, and rtl/ip/serial/uart.sv.
 - Hirosh Dabui: the original copyright notice is preserved in rtl/ip/memory/sdram_core.sv.
 - EmbedFire: attribution is preserved in the SPI SD card related files under rtl/ip/storage/.
+- Device simulation models: the models under rtl/model/ preserve their upstream
+  notices, including the Winbond Electronics Corporation notice in the
+  W25Q128JVxIM model.
 
 These notices are included solely to preserve attribution for the retained third-party source material. They do not alter the licensing terms of the retroSoC repository itself, which is distributed under the Mulan PSL v2 license.

dependencies/dependencies.lock.json

@@ -61,17 +61,12 @@
       "license": "Apache-2.0"
     },
     "cluster_archinfo": {"url": "https://github.com/retroSoC/archinfo.git", "revision": "78505969a0afdbc887cdd9b36eda228b4afb616e", "destination": "rtl/managed/clusterip/archinfo", "license": "MulanPSL-2.0"},
-    "cluster_clint": {"url": "https://github.com/retroSoC/clint.git", "revision": "ce49f1a5501c0a9f18c0e3f358417648f3f2fb18", "destination": "rtl/managed/clusterip/clint", "license": "NOASSERTION"},
     "cluster_common": {"url": "https://github.com/retroSoC/common.git", "revision": "5604bd5899bcc3a937cef55db4bac3b5102e562c", "destination": "rtl/managed/clusterip/common", "license": "NOASSERTION"},
     "cluster_crc": {"url": "https://github.com/retroSoC/crc.git", "revision": "8c1a5664c4d23d005c1afad432372a13ca967cc8", "destination": "rtl/managed/clusterip/crc", "license": "MulanPSL-2.0"},
-    "cluster_i2c": {"url": "https://github.com/retroSoC/i2c.git", "revision": "73b024547c5cd70fb8bf801cc7757db2536c604f", "destination": "rtl/managed/clusterip/i2c", "license": "NOASSERTION"},
-    "cluster_i2s": {"url": "https://github.com/retroSoC/i2s.git", "revision": "bd0978e8b45e4cf4c1335a1fa7311385d2a4e805", "destination": "rtl/managed/clusterip/i2s", "license": "NOASSERTION"},
-    "cluster_plic": {"url": "https://github.com/retroSoC/plic.git", "revision": "c851d93829d2e75b224003a058e718925855c0cc", "destination": "rtl/managed/clusterip/plic", "license": "NOASSERTION"},
     "cluster_ps2": {"url": "https://github.com/retroSoC/ps2.git", "revision": "2097a0d41b07573ff0453d65ba9a1670b3df7b9c", "destination": "rtl/managed/clusterip/ps2", "license": "MulanPSL-2.0"},
     "cluster_pwm": {"url": "https://github.com/retroSoC/pwm.git", "revision": "79ae32f725e848a1e7f6134847b3fb032ed64006", "destination": "rtl/managed/clusterip/pwm", "license": "MulanPSL-2.0"},
     "cluster_rng": {"url": "https://github.com/retroSoC/rng.git", "revision": "36f3e0774d8f3c4b597d3db8a96ca3992532b61e", "destination": "rtl/managed/clusterip/rng", "license": "MulanPSL-2.0"},
     "cluster_rtc": {"url": "https://github.com/retroSoC/rtc.git", "revision": "32548c5cbcdf39e09d0880fb611f9dd47940ea88", "destination": "rtl/managed/clusterip/rtc", "license": "NOASSERTION"},
-    "cluster_spi": {"url": "https://github.com/retroSoC/spi.git", "revision": "515cb408806584525605b4747db5e890dbdf1928", "destination": "rtl/managed/clusterip/spi", "license": "NOASSERTION"},
     "cluster_wdg": {"url": "https://github.com/retroSoC/wdg.git", "revision": "f5d39fa246054d678d34195824d943367dfcce44", "destination": "rtl/managed/clusterip/wdg", "license": "MulanPSL-2.0"}
   },
   "archives": {

rtl/README.md

@@ -5,8 +5,9 @@ peripheral and technology wrappers, filelists, testbench support, and the Mini
 SoC build entry points.
 
 `mini/` is the active SoC integration flow. `managed/` contains locked or
-vendored integration inputs, while `ip/` contains self-owned IP and
+vendored integration inputs, `ip/` contains self-owned IP and experiments, and
-experiments. `filelist/` selects PDK-specific RTL sources; `tech/` contains
+`model/` contains committed device simulation models with preserved upstream
+notices. `filelist/` selects PDK-specific RTL sources; `tech/` contains
 technology wrappers. Respect managed upstream boundaries and use setup helpers
 rather than editing generated MPW output.
 

rtl/ip/serial/i2c_if.sv

@@ -0,0 +1,33 @@
+// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
+// retroSoC is licensed under Mulan PSL v2.
+// See LICENSE for the complete license text.
+
+interface i2c_if ();
+  logic scl_i;
+  logic scl_o;
+  logic scl_oe_o;
+  logic sda_i;
+  logic sda_o;
+  logic sda_oe_o;
+  logic irq_o;
+
+  modport dut(
+      input scl_i,
+      output scl_o,
+      output scl_oe_o,
+      input sda_i,
+      output sda_o,
+      output sda_oe_o,
+      output irq_o
+  );
+
+  modport tb(
+      output scl_i,
+      input scl_o,
+      input scl_oe_o,
+      output sda_i,
+      input sda_o,
+      input sda_oe_o,
+      input irq_o
+  );
+endinterface

rtl/ip/storage/spi_if.sv

@@ -0,0 +1,23 @@
+// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
+// retroSoC is licensed under Mulan PSL v2.
+// See LICENSE for the complete license text.
+
+interface spi_if ();
+  logic sck_o;
+  logic nss_o;
+  logic mosi_o;
+  logic miso_i;
+  logic irq_o;
+
+  modport dut(output sck_o, output nss_o, output mosi_o, input miso_i, output irq_o);
+
+  // verilog_format: off -- preserve the signal-per-line testbench modport layout
+  modport tb(
+      input sck_o,
+      input nss_o,
+      input mosi_o,
+      output miso_i,
+      input irq_o
+  );
+  // verilog_format: on
+endinterface

rtl/mini/filelist/clusterip.fl

@@ -22,8 +22,6 @@
 /clusterip/ps2/rtl/ps2_reg.sv
 /clusterip/ps2/rtl/ps2_if.sv
 /clusterip/ps2/rtl/apb4_ps2.sv
-/clusterip/i2c/rtl/i2c_if.sv
-/clusterip/spi/rtl/spi_if.sv
 /clusterip/rtc/rtl/rtc_pkg.sv
 /clusterip/rtc/rtl/rtc_if.sv
 /clusterip/rtc/rtl/rtc_tickgen.sv

rtl/mini/filelist/inc.fl

@@ -9,8 +9,6 @@
 +incdir+/clusterip/rng/rtl
 +incdir+/clusterip/pwm/rtl
 +incdir+/clusterip/ps2/rtl
-+incdir+/clusterip/i2c/rtl
-+incdir+/clusterip/spi/rtl
 +incdir+/clusterip/rtc/rtl
 +incdir+/clusterip/wdg/rtl
 +incdir+/clusterip/crc/rtl

rtl/mini/filelist/ip.fl

@@ -14,6 +14,7 @@
 /ip/memory/opipsram_reg.sv
 /ip/memory/opipsram_if.sv
 /ip/memory/apb4_opipsram.sv
+/ip/storage/spi_if.sv
 /ip/storage/spisd_pkg.sv
 /ip/storage/spisd_define.svh
 /ip/storage/spisd_clock.sv
@@ -31,6 +32,7 @@
 /ip/storage/sdio_command.sv
 /ip/storage/sdio_data.sv
 /ip/storage/sdio_dma_descriptor.sv
+/ip/serial/i2c_if.sv
 /ip/serial/i2c_filter.sv
 /ip/serial/i2c_core.sv
 /ip/serial/i2c_reg.sv

rtl/mini/filelist/tb.fl

@@ -1,8 +1,8 @@
 /clusterip/ps2/dv/model/ps2_device_model.sv
-/clusterip/i2c/model/at24cxxx.sv
+/device_model/at24cxxx.sv
 /model/uart_model.sv
-/clusterip/i2s/model/mic.sv
+/device_model/mic.sv
-/clusterip/spi/model/w25q128jvxim.sv
+/device_model/w25q128jvxim.sv
 /model/ESP_PSRAM64H.sv
 /model/DVP_CAMERA.sv
 /third_party/model/sdram/sdr.v

rtl/mini/formal/generate_formal_filelist.py

@@ -142,7 +142,7 @@ def source_files(target: str) -> list[Path]:
             COMMON_RTL / "utils/register.sv",
             COMMON_RTL / "utils/fifo.sv",
             COMMON_RTL / "cdc/cdc_sync.sv",
-            ROOT / "rtl/managed/clusterip/i2c/rtl/i2c_if.sv",
+            SERIAL / "i2c_if.sv",
             SERIAL / "i2c_filter.sv",
             SERIAL / "i2c_core.sv",
             SERIAL / "i2c_reg.sv",

rtl/mini/lint.msg

@@ -1,5 +1,5 @@
 { 
     +lint=all;
-    -file=/hazard3/arith/hazard3_muldiv_seq.v,/hazard3/hazard3_frontend.v,/hazard3/arith/hazard3_onehot_encode.v,/hazard3/hazard3_instr_decompress.v,/physical/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/verilog/icsIOA_N55_3P3.v,/physical/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/verilog/ics55_LLSC_H7CR.v,/physical/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/verilog/ics55_LLSC_H7CL.v,/physical/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CH/verilog/ics55_LLSC_H7CH.v,/physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v,/clusterip/i2c/model/at24cxxx.sv,/clusterip/spi/model/w25q128jvxim.sv,/clusterip/common/rtl/cdc/cdc_2phase.sv,/clusterip/common/rtl/utils/register.sv,/model/uart_model.sv,/tb/retrosoc_tb.sv,/clusterip/i2s/model/mic.sv,/model/ESP_PSRAM64H.sv,/third_party/model/sdram/sdr.v;
+    -file=/hazard3/arith/hazard3_muldiv_seq.v,/hazard3/hazard3_frontend.v,/hazard3/arith/hazard3_onehot_encode.v,/hazard3/hazard3_instr_decompress.v,/physical/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/verilog/icsIOA_N55_3P3.v,/physical/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/verilog/ics55_LLSC_H7CR.v,/physical/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/verilog/ics55_LLSC_H7CL.v,/physical/pdk/icsprout55-pdk/IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CH/verilog/ics55_LLSC_H7CH.v,/physical/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v,/device_model/at24cxxx.sv,/device_model/w25q128jvxim.sv,/clusterip/common/rtl/cdc/cdc_2phase.sv,/clusterip/common/rtl/utils/register.sv,/model/uart_model.sv,/tb/retrosoc_tb.sv,/device_model/mic.sv,/model/ESP_PSRAM64H.sv,/third_party/model/sdram/sdr.v;
 }
 { +warn=all; }

rtl/mini/mk/formal.mk

@@ -98,7 +98,7 @@ FORMAL_SOURCE_FILES          := $(RTL_PATH)/formal/bus_formal.sv \
                              $(ROOT_PATH)/rtl/ip/serial/i2s_define.svh \
                              $(ROOT_PATH)/rtl/ip/serial/i2s_pkg.sv \
                              $(ROOT_PATH)/rtl/ip/serial/i2s_reg.sv \
-                             $(ROOT_PATH)/rtl/managed/clusterip/i2c/rtl/i2c_if.sv \
+                             $(ROOT_PATH)/rtl/ip/serial/i2c_if.sv \
                              $(ROOT_PATH)/rtl/ip/peripheral/timer_core.sv \
                              $(ROOT_PATH)/rtl/ip/peripheral/timer_define.svh \
                              $(ROOT_PATH)/rtl/ip/peripheral/timer_reg.sv \

rtl/mini/script/generate_filelist.py

@@ -26,6 +26,7 @@ PATH_PREFIXES = {
     "hazard3": RTL_DIR / "managed" / "hazard3" / "hdl",
     "mpw": RTL_DIR / "managed" / "mpw",
     "tb": MINI_DIR / "dv" / "tb",
+    "device_model": RTL_DIR / "model",
     "model": MINI_DIR / "dv" / "model",
     "sva": MINI_DIR / "dv" / "sva",
     "top": MINI_DIR / "top",

rtl/model/README.md

@@ -0,0 +1,16 @@
+# Device Simulation Models
+
+This directory contains committed device models used only by retroSoC simulation.
+The models are excluded from the self-owned synthesizable RTL style profile and
+retain their upstream notices and behavior. The repository import normalizes
+line endings and trailing whitespace.
+
+| File | Upstream source | Revision | Upstream SHA-256 |
+| --- | --- | --- | --- |
+| `at24cxxx.sv` | `https://github.com/retroSoC/i2c.git` | `73b024547c5cd70fb8bf801cc7757db2536c604f` | `636ed7e58574735a80943122178da8e1b23a48d443ec11d96ccdbd8618da404b` |
+| `mic.sv` | `https://github.com/retroSoC/i2s.git` | `bd0978e8b45e4cf4c1335a1fa7311385d2a4e805` | `2d5264092bac13f28c5e38cfba4a9288afb6d704c7821f40265177c32715a6b3` |
+| `w25q128jvxim.sv` | `https://github.com/retroSoC/spi.git` | `515cb408806584525605b4747db5e890dbdf1928` | `4b95f007a39854dc2690cf0b608b1b4b56a61adbf1e7c736e7ab5d44d46a112f` |
+
+The Winbond model retains its upstream copyright and "All Rights Reserved"
+notice. Inclusion here records provenance and does not relicense that model
+under the retroSoC project license.

rtl/model/mic.sv

@@ -0,0 +1,38 @@
+// Copyright (c) 2023-2024 Miao Yuchi <miaoyuchi@ict.ac.cn>
+// i2s is licensed under Mulan PSL v2.
+// You can use this software according to the terms and conditions of the Mulan PSL v2.
+// You may obtain a copy of Mulan PSL v2 at:
+//             http://license.coscl.org.cn/MulanPSL2
+// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+// See the Mulan PSL v2 for more details.
+
+`include "config.svh"
+
+module mic #(
+    parameter int DATA_WIDTH = 24
+) (
+    input  logic sck_i,
+    input  logic ws_i,
+    output logic sd_o
+);
+
+  logic [DATA_WIDTH-1:0] r_right_chnl_dat = '0;
+  logic [DATA_WIDTH-1:0] r_left_chnl_dat = '0;
+  logic                  r_ws = '0;
+
+  always @(posedge sck_i) r_ws <= #`REGISTER_DELAY ws_i;
+  always @(negedge r_ws) r_left_chnl_dat <= #`REGISTER_DELAY $random;
+  always @(posedge r_ws) r_right_chnl_dat <= #`REGISTER_DELAY $random;
+
+  always @(negedge sck_i)
+    if (~r_ws) begin
+      sd_o            <= #`REGISTER_DELAY r_left_chnl_dat[DATA_WIDTH-1];
+      r_left_chnl_dat <= #`REGISTER_DELAY r_left_chnl_dat << 1;
+    end else begin
+      sd_o             <= #`REGISTER_DELAY r_right_chnl_dat[DATA_WIDTH-1];
+      r_right_chnl_dat <= #`REGISTER_DELAY r_right_chnl_dat << 1;
+    end
+
+endmodule

rtl/rtl_style_audit.json

@@ -180,6 +180,7 @@
       "apb4_ws2812.sv",
       "i2c_core.sv",
       "i2c_filter.sv",
+      "i2c_if.sv",
       "i2c_reg.sv",
       "i2s_clkgen.sv",
       "i2s_core.sv",
@@ -225,6 +226,7 @@
       "sdio_if.sv",
       "sdio_pkg.sv",
       "sdio_reg.sv",
+      "spi_if.sv",
       "spisd_clock.sv",
       "spisd_command.sv",
       "spisd_core.sv",

tests/test_i2c.py

@@ -19,7 +19,6 @@ def test_i2c_controller_and_recovery_contract(tmp_path: Path) -> None:
 
     common = ROOT / "rtl/managed/clusterip/common/rtl"
     serial = ROOT / "rtl/ip/serial"
-    cluster_i2c = ROOT / "rtl/managed/clusterip/i2c/rtl"
     source_list = tmp_path / "i2c.fl"
     source_list.write_text(
         "\n".join(
@@ -34,7 +33,7 @@ def test_i2c_controller_and_recovery_contract(tmp_path: Path) -> None:
                 str(common / "utils/register.sv"),
                 str(common / "utils/fifo.sv"),
                 str(common / "cdc/cdc_sync.sv"),
-                str(cluster_i2c / "i2c_if.sv"),
+                str(serial / "i2c_if.sv"),
                 str(serial / "i2c_filter.sv"),
                 str(serial / "i2c_core.sv"),
                 str(serial / "i2c_reg.sv"),

tests/test_spisd.py

@@ -14,7 +14,6 @@ COMMON_REGISTER = "rtl/managed/clusterip/common/rtl/utils/register.sv"
 INCDIRS = [
     "rtl/managed/clusterip/common/rtl",
     "rtl/managed/clusterip/common/rtl/interface",
-    "rtl/managed/clusterip/spi/rtl",
     "rtl/ip/peripheral",
     "rtl/ip/storage",
 ]
@@ -108,7 +107,7 @@ def test_spisd_wrapper_apb_and_training() -> None:
         [
             "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv",
             "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv",
-            "rtl/managed/clusterip/spi/rtl/spi_if.sv",
+            "rtl/ip/storage/spi_if.sv",
             "rtl/ip/storage/spisd_pkg.sv",
             "rtl/ip/storage/spisd_define.svh",
             COMMON_REGISTER,