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fix: fix a error tim value reg wr bit width bug

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maksyuki committed 2025-02-01 00:10:07 +08:00
1 parent b7946628e0
commit 41a21b6881
3 files changed
+7 -5
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rtl/ip/apb_wrapper.v
+2
View File
@@ -0,0 +1,2 @@
module apb_wrapper ();
endmodule
rtl/ip/counter_timer.v
+4 -4
View File
@@ -48,10 +48,10 @@ module counter_timer (
if (resetn == 1'b0) begin
value_reset <= 32'd0;
end else begin
if (reg_val_we[3]) value_reset <= reg_val_di[31:24];
if (reg_val_we[2]) value_reset <= reg_val_di[23:16];
if (reg_val_we[1]) value_reset <= reg_val_di[15:8];
if (reg_val_we[0]) value_reset <= reg_val_di[7:0];
if (reg_val_we[3]) value_reset[31:24] <= reg_val_di[31:24];
if (reg_val_we[2]) value_reset[23:16] <= reg_val_di[23:16];
if (reg_val_we[1]) value_reset[15:8] <= reg_val_di[15:8];
if (reg_val_we[0]) value_reset[7:0] <= reg_val_di[7:0];
end
end
rtl/ip/i2c_slave.v
+1 -1
View File
@@ -55,7 +55,7 @@ module i2c_slave (
if (cntr == 8) state = SDATA;
else if ((state == SDATA) && (cntr == 17)) begin
state <= SIDLE;
$display("i2c Slave has received 0x%X - Address: 0x%X", data, addr);
$display("[HARDWARE] i2c Slave has received 0x%X - Address: 0x%X", data, addr);
end
initial begin